user/sven/linux-2.4.git, branch master

Relax si_code check in rt_sigqueueinfo and rt_tgsigqueueinfo

2012-10-05T22:35:00Z

commit 243b422af9ea9af4ead07a8ad54c90d4f9b6081a upstream Commit da48524eb206 ("Prevent rt_sigqueueinfo and rt_tgsigqueueinfo from spoofing the signal code") made the check on si_code too strict. There are several legitimate places where glibc wants to queue a negative si_code different from SI_QUEUE: - This was first noticed with glibc's aio implementation, which wants to queue a signal with si_code SI_ASYNCIO; the current kernel causes glibc's tst-aio4 test to fail because rt_sigqueueinfo() fails with EPERM. - Further examination of the glibc source shows that getaddrinfo_a() wants to use SI_ASYNCNL (which the kernel does not even define). The timer_create() fallback code wants to queue signals with SI_TIMER. As suggested by Oleg Nesterov , loosen the check to forbid only the problematic SI_TKILL case. Reported-by: Klaus Dittrich Acked-by: Julien Tinnes Cc: Signed-off-by: Roland Dreier Signed-off-by: Linus Torvalds Tested-by: Krzysztof Mazur Signed-off-by: Willy Tarreau

8xx: The TLB miss handler manages ACCESSED correctly.

2012-04-09T13:02:41Z

The new MMU/TLB code no longer sets ACCESSED unconditionally so remove the exception. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau

8xx: Optimize TLB Miss handlers

2012-04-09T13:02:41Z

Only update pte w.r.t ACCESSED if it isn't already set Wrap ACCESSED with #ifndef NO_SWAP for too ease optimization. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau

8xx: Use symbolic constants in TLB asm

2012-04-09T13:02:41Z

Use the PTE #defines where possible instead of hardcoded constants. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau

8xx: start using dcbX instructions in various copy routines

2012-04-09T13:02:40Z

Now that 8xx can fixup dcbX instructions, start using them where possible like every other PowerPc arch do. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau

8xx: Set correct HW pte flags in DTLB Error too

2012-04-09T13:02:40Z

DTLB Error needs to adjust the HW PTE bits as DTLB Miss does. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau

8xx: Restore _PAGE_WRITETHRU

2012-04-09T13:02:40Z

8xx has not had WRITETHRU due to lack of bits in the pte. After the recent rewrite of the 8xx TLB code, there are two bits left. Use one of them to WRITETHRU. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau

8xx: Add missing Guarded setting in DTLB Error.

2012-04-09T13:02:40Z

only DTLB Miss did set this bit, DTLB Error needs too otherwise the setting is lost when the page becomes dirty. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau

8xx: CPU6 errata make DTLB error too big to fit.

2012-04-09T13:02:40Z

branch to common code in DTLB Miss instead. Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau

8xx: Fixup DAR from buggy dcbX instructions.

2012-04-09T13:02:39Z

This is an assembler version to fixup DAR not being set by dcbX, icbi instructions. There are two versions, one uses selfmodifing code, the other uses a jump table but is much bigger(default). Signed-off-by: Joakim Tjernlund Signed-off-by: Willy Tarreau