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<title>user/sven/linux.git, branch v5.10.23</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.10.23</id>
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<updated>2021-03-11T13:17:30Z</updated>
<entry>
<title>Linux 5.10.23</title>
<updated>2021-03-11T13:17:30Z</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2021-03-11T13:17:30Z</published>
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<id>urn:sha1:dfbf345b63c31518e269f7f0adf55bbf57017e23</id>
<content type='text'>
Tested-by: Hulk Robot &lt;hulkrobot@huawei.com&gt;
Tested-by: Pavel Machek (CIP) &lt;pavel@denx.de&gt;
Tested-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;
Tested-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
Tested-by: Jason Self &lt;jason@bluehome.net&gt;
Tested-by: Ross Schmidt &lt;ross.schm.dev@gmail.com&gt;
Tested-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Tested-by: Linux Kernel Functional Testing &lt;lkft@linaro.org&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://lore.kernel.org/r/20210310182834.696191666@linuxfoundation.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>nvme-pci: add quirks for Lexar 256GB SSD</title>
<updated>2021-03-11T13:17:30Z</updated>
<author>
<name>Pascal Terjan</name>
<email>pterjan@google.com</email>
</author>
<published>2021-02-23T22:10:46Z</published>
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<id>urn:sha1:c8714d1faae829ebb4139c73bcbc0d66fd7edbc9</id>
<content type='text'>
[ Upstream commit 6e6a6828c517fb6819479bf5187df5f39084eb9e ]

Add the NVME_QUIRK_NO_NS_DESC_LIST and NVME_QUIRK_IGNORE_DEV_SUBNQN
quirks for this buggy device.

Reported and tested in https://bugs.mageia.org/show_bug.cgi?id=28417

Signed-off-by: Pascal Terjan &lt;pterjan@google.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>nvme-pci: mark Seagate Nytro XM1440 as QUIRK_NO_NS_DESC_LIST.</title>
<updated>2021-03-11T13:17:29Z</updated>
<author>
<name>Julian Einwag</name>
<email>jeinwag-nvme@marcapo.com</email>
</author>
<published>2021-02-16T12:25:43Z</published>
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<id>urn:sha1:e88e01440a480d2d30d18657ab9a2e2f2e4c23a8</id>
<content type='text'>
[ Upstream commit 5e112d3fb89703a4981ded60561b5647db3693bf ]

The kernel fails to fully detect these SSDs, only the character devices
are present:

[   10.785605] nvme nvme0: pci function 0000:04:00.0
[   10.876787] nvme nvme1: pci function 0000:81:00.0
[   13.198614] nvme nvme0: missing or invalid SUBNQN field.
[   13.198658] nvme nvme1: missing or invalid SUBNQN field.
[   13.206896] nvme nvme0: Shutdown timeout set to 20 seconds
[   13.215035] nvme nvme1: Shutdown timeout set to 20 seconds
[   13.225407] nvme nvme0: 16/0/0 default/read/poll queues
[   13.233602] nvme nvme1: 16/0/0 default/read/poll queues
[   13.239627] nvme nvme0: Identify Descriptors failed (8194)
[   13.246315] nvme nvme1: Identify Descriptors failed (8194)

Adding the NVME_QUIRK_NO_NS_DESC_LIST fixes this problem.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=205679
Signed-off-by: Julian Einwag &lt;jeinwag-nvme@marcapo.com&gt;
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Keith Busch &lt;kbusch@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>KVM: SVM: Clear the CR4 register on reset</title>
<updated>2021-03-11T13:17:29Z</updated>
<author>
<name>Babu Moger</name>
<email>babu.moger@amd.com</email>
</author>
<published>2021-03-02T18:51:31Z</published>
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<id>urn:sha1:3b659091587a39bc581e0cf2775b03d18ed97fa7</id>
<content type='text'>
[ Upstream commit 9e46f6c6c959d9bb45445c2e8f04a75324a0dfd0 ]

This problem was reported on a SVM guest while executing kexec.
Kexec fails to load the new kernel when the PCID feature is enabled.

When kexec starts loading the new kernel, it starts the process by
resetting the vCPU's and then bringing each vCPU online one by one.
The vCPU reset is supposed to reset all the register states before the
vCPUs are brought online. However, the CR4 register is not reset during
this process. If this register is already setup during the last boot,
all the flags can remain intact. The X86_CR4_PCIDE bit can only be
enabled in long mode. So, it must be enabled much later in SMP
initialization.  Having the X86_CR4_PCIDE bit set during SMP boot can
cause a boot failures.

Fix the issue by resetting the CR4 register in init_vmcb().

Signed-off-by: Babu Moger &lt;babu.moger@amd.com&gt;
Message-Id: &lt;161471109108.30811.6392805173629704166.stgit@bmoger-ubuntu&gt;
Signed-off-by: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: Fix a duplicate dev quirk number</title>
<updated>2021-03-11T13:17:29Z</updated>
<author>
<name>Avri Altman</name>
<email>avri.altman@wdc.com</email>
</author>
<published>2021-02-11T10:46:38Z</published>
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<id>urn:sha1:1611c323df9f5ddfc1ed36c9deec6052da9d40df</id>
<content type='text'>
[ Upstream commit 9599a1cf23330008d90b7c232efe95de7510ff29 ]

Fixes: 2b2bfc8aa519 ("scsi: ufs: Introduce a quirk to allow only page-aligned sg entries")
Link: https://lore.kernel.org/r/20210211104638.292499-1-avri.altman@wdc.com
Reviewed-by: Bean Huo &lt;beanhuo@micron.com&gt;
Signed-off-by: Avri Altman &lt;avri.altman@wdc.com&gt;
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: Intel: sof_sdw: add quirk for HP Spectre x360 convertible</title>
<updated>2021-03-11T13:17:29Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2021-02-08T23:33:28Z</published>
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<id>urn:sha1:2dba0f805416ef88c0fa4c3e4c5603aa4078e329</id>
<content type='text'>
[ Upstream commit d92e279dee56b4b65c1af21f972413f172a9734a ]

This set of devices has SoundWire support along with DMICs.
The DMI information was provided by users for 3 separate skus.

BugLink: https://github.com/thesofproject/linux/issues/2700
Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Guennadi Liakhovetski &lt;guennadi.liakhovetski@intel.com&gt;
Reviewed-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20210208233336.59449-4-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ASoC: Intel: sof_sdw: reorganize quirks by generation</title>
<updated>2021-03-11T13:17:29Z</updated>
<author>
<name>Pierre-Louis Bossart</name>
<email>pierre-louis.bossart@linux.intel.com</email>
</author>
<published>2021-02-08T23:33:26Z</published>
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<id>urn:sha1:c08344abc9714f7ea43f338a177031d5ec1bcde3</id>
<content type='text'>
[ Upstream commit 3d09cf8d0d791a41a75123e135f604d59f4aa870 ]

The quirk table is a mess, let's reorganize it by generation before
making sure that the quirks are consistent for each generation.

Signed-off-by: Pierre-Louis Bossart &lt;pierre-louis.bossart@linux.intel.com&gt;
Reviewed-by: Guennadi Liakhovetski &lt;guennadi.liakhovetski@intel.com&gt;
Reviewed-by: Kai Vehmanen &lt;kai.vehmanen@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20210208233336.59449-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown &lt;broonie@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>PCI: cadence: Retrain Link to work around Gen2 training defect</title>
<updated>2021-03-11T13:17:29Z</updated>
<author>
<name>Nadeem Athani</name>
<email>nadeem@cadence.com</email>
</author>
<published>2021-02-09T14:46:21Z</published>
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<id>urn:sha1:1d3efd15e8a43ce2ea91c040f77ef67a0b2b3bc5</id>
<content type='text'>
[ Upstream commit 4740b969aaf58adeca6829947a3ad8da423976cf ]

Cadence controller will not initiate autonomous speed change if strapped
as Gen2. The Retrain Link bit is set as quirk to enable this speed change.

Link: https://lore.kernel.org/r/20210209144622.26683-3-nadeem@cadence.com
Signed-off-by: Nadeem Athani &lt;nadeem@cadence.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ALSA: usb-audio: add mixer quirks for Pioneer DJM-900NXS2</title>
<updated>2021-03-11T13:17:28Z</updated>
<author>
<name>Fabian Lesniak</name>
<email>fabian@lesniak-it.de</email>
</author>
<published>2021-02-05T21:51:16Z</published>
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<id>urn:sha1:015d38539db9121147682380111f7a460eb46df4</id>
<content type='text'>
[ Upstream commit fee03efc69345344c8851596d74d93199b175bfe ]

This commit adds mixer quirks for the Pioneer DJM-900NXS2 mixer. This
device has 6 capture channels, 5 of them allow setting the signal
source. This adds controls for these, similar to the DJM-250Mk2.
However, playpack channels are not controllable via software like on the
250Mk2, as they can only be set manually on the mixing console.
Read-only controls showing the currently selected playback channels are
omitted.

Signed-off-by: Fabian Lesniak &lt;fabian@lesniak-it.de&gt;
Link: https://lore.kernel.org/r/20210205215116.258724-2-fabian@lesniak-it.de
Signed-off-by: Takashi Iwai &lt;tiwai@suse.de&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ALSA: usb-audio: Add DJM750 to Pioneer mixer quirk</title>
<updated>2021-03-11T13:17:28Z</updated>
<author>
<name>Olivia Mackintosh</name>
<email>livvy@base.nu</email>
</author>
<published>2021-02-05T18:42:56Z</published>
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<id>urn:sha1:d78acca2afe50a73e89617732ba029098e7abaac</id>
<content type='text'>
[ Upstream commit a07df82c799013236aa90a140785775eda9f9523 ]

This allows for N different devices to use the pioneer mixer quirk for
setting capture/record type and recording level. The impementation has
not changed much with the exception of an additional mask on
private_value to allow storing of a device index:
	DEVICE MASK	0xff000000
	GROUP_MASK	0x00ff0000
	VALUE_MASK	0x0000ffff

This could be improved by changing the arrays of wValues for each
channel to contain named definitions (e.g. SND_DJM_CAP_LINE). It would
improve readability and perhaps would allow using the same array for
multiple channels. The channel number can be specified on the control
next to the wIndex.

Feedback is very much appreciated as I'm not the most proficient C
programmer but am learning as I go.

Signed-off-by: Olivia Mackintosh &lt;livvy@base.nu&gt;
Link: https://lore.kernel.org/r/20210205184256.10201-2-livvy@base.nu
Signed-off-by: Takashi Iwai &lt;tiwai@suse.de&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
</feed>
