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<title>user/sven/linux.git/Documentation/devicetree/bindings/dma, branch v4.4</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.4</id>
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<updated>2015-12-10T03:02:42Z</updated>
<entry>
<title>dmaengine: edma: DT: Change reserved slot array from 16bit to 32bit type</title>
<updated>2015-12-10T03:02:42Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-12-09T08:18:11Z</published>
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<id>urn:sha1:ae0add740cd06169cd124f9aaa6eceb11e5b3060</id>
<content type='text'>
This change makes the DT file to be easier to read since the reserved slots
array does not need the '/bits/ 16' to be specified, which might confuse
some people.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: edma: DT: Change memcpy channel array from 16bit to 32bit type</title>
<updated>2015-12-10T03:01:10Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-12-09T08:18:10Z</published>
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<id>urn:sha1:ecb7deceff2a51d3be50518969bc06411f485a62</id>
<content type='text'>
This change makes the DT file to be easier to read since the memcpy
channels array does not need the '/bits/ 16' to be specified, which might
confuse some people.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: edma: New device tree binding</title>
<updated>2015-10-27T01:22:45Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-10-16T07:18:10Z</published>
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<id>urn:sha1:1be5336bc7ba050ee07d352643bf4c01c513553c</id>
<content type='text'>
With the old binding and driver architecture we had many issues:
No way to assign eDMA channels to event queues, thus not able to tune the
system by moving specific DMA channels to low/high priority servicing. We
moved the cyclic channels to high priority within the code, but that was
just a workaround to this issue.
Memcopy was fundamentally broken: even if the driver scanned the DT/devices
in the booted system for direct DMA users (which is not effective when the
events are going through a crossbar) and created a map of 'used' channels,
this information was not really usable. Since via dmaengien API the eDMA
driver will be called with _some_ channel number, we would try to request
this channel when any channel is requested for memcpy. By luck we got
channel which is not used by any device most of the time so things worked,
but if a device would have been using the given channel, but not requested
it, the memcpy channel would have been waiting for HW event.
The old code had the am33xx/am43xx DMA event router handling embedded. This
should have been done in a separate driver since it is not part of the
actual eDMA IP.
There were no way to 'lock' PaRAM slots to be used by the DSP for example
when booting with DT.
In DT boot the edma node used more than one hwmod which is not a good
practice and the kernel prints warning because of this.

With the new bindings and the changes in the driver we can:
- No regression with Legacy binding and non DT boot
- DMA channels can be assigned to any TC (to set priority)
- PaRAM slots can be reserved for other cores to use
- Dynamic power management for CC and TCs, if only TC0 is used all other TC
  can be powered down for example

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: ti-dma-crossbar: Add support for crossbar on AM33xx/AM43xx</title>
<updated>2015-10-27T01:22:45Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-10-16T07:18:08Z</published>
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<id>urn:sha1:42dbdcc6bf965997c088caff2a8be7f9bf44f701</id>
<content type='text'>
The DMA event crossbar on AM33xx/AM43xx is different from the one found in
DRA7x family.
Instead of a single event crossbar it has 64 identical mux attached to each
eDMA event line. When the 0 event mux is selected, the default mapped event
is going to be routed to the corresponding eDMA event line. If different
mux is selected, then the selected event is going to be routed to the given
eDMA event.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma</title>
<updated>2015-09-04T18:10:18Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2015-09-04T18:10:18Z</published>
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<id>urn:sha1:352712274507645b6f82b8763977ad87321919a3</id>
<content type='text'>
Pull dmaengine updates from Vinod Koul:
 "This time we have aded a new capability for scatter-gathered memset
  using dmaengine APIs.  This is supported in xdmac &amp; hdmac drivers

  We have added support for reusing descriptors for examples like video
  buffers etc.  Driver will follow

  The behaviour of descriptor ack has been clarified and documented

  New devices added are:
   - dma controller in sun[457]i SoCs
   - lpc18xx dmamux
   - ZTE ZX296702 dma controller
   - Analog Devices AXI-DMAC DMA controller
   - eDMA support for dma-crossbar
   - imx6sx support in imx-sdma driver
   - imx-sdma device to device support

  Other:
   - jz4780 fixes
   - ioatdma large refactor and cleanup for removal of ioat v1 and v2
     which is deprecated and fixes
   - ACPI support in X-Gene DMA engine driver
   - ipu irq fixes
   - mvxor fixes
   - minor fixes spread thru drivers"

[ The Kconfig and Makefile entries got re-sorted alphabetically, and I
  handled the conflict with the new Intel integrated IDMA driver by
  slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in
  order to keep the Intel entries together.  I think it might be a good
  idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make
  the sorting be a true sort, not this mismash.

  Also, this merge disables the COMPILE_TEST for the sun4i DMA
  controller, because it does not compile cleanly at all.     - Linus ]

* tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits)
  dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs
  dmaengine :ipu: change ipu_irq_handler() to remove compile warning
  dmaengine: ioatdma: Fix variable array length
  dmaengine: ioatdma: fix sparse "error" with prep lock
  dmaengine: hdmac: Add memset capabilities
  dmaengine: sort the sh Makefile
  dmaengine: sort the sh Kconfig
  dmaengine: sort the dw Kconfig
  dmaengine: sort the Kconfig
  dmaengine: sort the makefile
  drivers/dma: make mv_xor.c driver explicitly non-modular
  dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller
  devicetree: Add bindings documentation for Analog Devices AXI-DMAC
  dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests
  dmaengine: ioatdma: fix coccinelle warning
  dmaengine: ioatdma: fix zero day warning on incompatible pointer type
  dmaengine: tegra-apb: Simplify locking for device using global pause
  dmaengine: tegra-apb: Remove unnecessary return statements and variables
  dmaengine: tegra-apb: Avoid unnecessary channel base address calculation
  dmaengine: tegra-apb: Remove unused variables
  ...
</content>
</entry>
<entry>
<title>devicetree: Add bindings documentation for Analog Devices AXI-DMAC</title>
<updated>2015-08-23T13:25:10Z</updated>
<author>
<name>Lars-Peter Clausen</name>
<email>lars@metafoo.de</email>
</author>
<published>2015-08-20T15:39:12Z</published>
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<id>urn:sha1:43bcad2bb485f053661e5cfe306c34178c6651c7</id>
<content type='text'>
Add the devicetree descriptor for the Analog Devices AXI-DMAC DMA
controller. This is a soft peripheral used in FPGAs and the bindings
describe how it is connected to the system (clock, interrupt, memory map)
as well as the configuration options that were used when the peripheral was
instantiated.

Signed-off-by: Lars-Peter Clausen &lt;lars@metafoo.de&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'topic/zxdma' into for-linus</title>
<updated>2015-08-23T13:24:39Z</updated>
<author>
<name>Vinod Koul</name>
<email>vinod.koul@intel.com</email>
</author>
<published>2015-08-23T13:24:39Z</published>
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<id>urn:sha1:b2b48ac4c584ae31eb23ad1f86964cc6e52eaa54</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dmaengine: sun4i: Add support for the DMA engine on sun[457]i SoCs</title>
<updated>2015-08-20T05:15:19Z</updated>
<author>
<name>Emilio López</name>
<email>emilio@elopez.com.ar</email>
</author>
<published>2015-07-26T20:50:55Z</published>
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<id>urn:sha1:b096c1377d1e50cea91d1db13bca8e7802199a67</id>
<content type='text'>
This patch adds support for the DMA engine present on Allwinner A10,
A13, A10S and A20 SoCs. This engine has two kinds of channels: normal
and dedicated. The main difference is in the mode of operation;
while a single normal channel may be operating at any given time,
dedicated channels may operate simultaneously provided there is no
overlap of source or destination.

Hardware documentation can be found on A10 User Manual (section 12), A13
User Manual (section 14) and A20 User Manual (section 1.12)

Signed-off-by: Emilio López &lt;emilio@elopez.com.ar&gt;
Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: mv_xor: remove support for dmacap,* DT properties</title>
<updated>2015-08-19T17:01:53Z</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2015-07-08T14:28:16Z</published>
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<id>urn:sha1:6d8f7abd235c1a38629cdada49cc53992f4ad42e</id>
<content type='text'>
The only reason why we had dmacap,* properties is because back when
DMA_MEMSET was supported, only one out of the two channels per engine
could do a memset operation. But this is something that the driver
already knows anyway, and since then, the DMA_MEMSET support has been
removed.

The driver is already well aware of what each channel supports and the
one to one mapping between Linux specific implementation details (such
as dmacap,interrupt enabling DMA_INTERRUPT) and DT properties is a
good indication that these DT properties are wrong.

Therefore, this commit simply gets rid of these dmacap,* properties,
they are now ignored, and the driver is responsible for knowing the
capabilities of the hardware with regard to the dmaengine subsystem
expectations.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Reviewed-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>doc: dt: dma: add bindings for lpc1850-dmamux</title>
<updated>2015-08-18T16:42:14Z</updated>
<author>
<name>Joachim Eastwood</name>
<email>manabian@gmail.com</email>
</author>
<published>2015-07-11T12:12:07Z</published>
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<id>urn:sha1:df48f3ff95c432cc3469e0df67da76ffcf2237af</id>
<content type='text'>
Add device tree bindings documentation for the
lpc1850-dmamux DMA router.

Signed-off-by: Joachim Eastwood &lt;manabian@gmail.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
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