user/sven/linux.git/Documentation/gpu/amdgpu, branch v6.1.167

Documentation/gpu: Add Multiplane Overlay doc

2022-09-01T19:09:46Z

Multiple plane overlay is a feature supported by AMD hardware, but it has specific details that deserve proper documentation. This commit introduces a documentation that describes some of the features, limitations, and use cases for this feature. Part of this documentation came from some discussion in the public upstream [1][2]. [1]. https://lore.kernel.org/amd-gfx/3qY-QeukF_Q_MJeIXAuBjO4szbS4jRtqkTifXnbnN3bp88SxVodFQRpah3mIIVJq24DUkF6g0rOGdCmSqTvVxx9LCGEItmzLw8uWU44jtXE=@emersion.fr/ [2]. https://lore.kernel.org/amd-gfx/864e45d0-c14b-3b12-0f5b-9d26a9cb41bd@amd.com/ Cc: Harry Wentland Cc: Nicholas Kazlauskas Cc: Bhawanpreet Lakha Cc: Hersen Wu Cc: Alex Hung Cc: Pierre-Eric Pelloux-Prayer Cc: Simon Ser Cc: Pekka Paalanen Cc: Sean Paul Cc: Mark Yacoub Cc: Leo Li Cc: Pierre-Loup Cc: Michel Dänzer Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

Documentation/gpu: Add an explanation about the DCN pipeline

2022-09-01T19:09:39Z

In the DCN code, we constantly talk about hardware pipeline, pipeline, or even just pipes, which is a concept that is not obvious to everyone. For this reason, this commit expands the DCN overview explanation by adding a new section that describes what a pipeline is from the DCN perspective. Changes since V1: - Rewrite the first paragraph that describes AMD hardware pipeline. Cc: Harry Wentland Cc: Nicholas Kazlauskas Cc: Bhawanpreet Lakha Cc: Hersen Wu Cc: Alex Hung Cc: Pierre-Eric Pelloux-Prayer Cc: Leo Li Cc: Simon Ser Cc: Pekka Paalanen Cc: Sean Paul Cc: Mark Yacoub Cc: Pierre-Loup Cc: Michel Dänzer Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

Documentation/gpu: Add info table for ASICs

2022-09-01T19:09:31Z

Amdgpu driver is used in an extensive range of devices, and each ASIC has some specific configuration. As a result of this variety, sometimes it is hard to identify the correct block that might cause the issue. This commit expands the amdgpu kernel-doc to alleviate this issue by introducing one ASIC table that describes dGPU and another one that shares the APU info. Cc: Harry Wentland Cc: Nicholas Kazlauskas Cc: Bhawanpreet Lakha Cc: Hersen Wu Cc: Alex Hung Cc: Pierre-Eric Pelloux-Prayer Cc: Leo Li Cc: Simon Ser Cc: Pekka Paalanen Cc: Sean Paul Cc: Mark Yacoub Cc: Pierre-Loup Cc: Michel Dänzer Cc: Kent Russell Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

Documentation/gpu: Document GFXOFF's count and residency

2022-08-16T22:17:32Z

Add documentation explaining those two new files. While here, add a note about the value type. Signed-off-by: André Almeida Signed-off-by: Alex Deucher

Documentation/gpu/amdgpu/amdgpu_dm: add DM docs for pixel blend mode

2022-08-16T22:14:32Z

AMD GPU display manager (DM) maps DRM pixel blend modes (None, Pre-multiplied, Coverage) to MPC hw blocks through blend configuration options. Describe relevant elements and how to set and test them to get the expected DRM blend mode on DCN hw. v2: - add ref tag (Tales) Signed-off-by: Melissa Wen Reviewed-by: Tales Aparecida Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: add doc entries for MPC blending configuration

2022-08-16T22:14:32Z

Describe structs and enums used to set blend mode properties to MPC blocks. Some pieces of information are already available as code comments, and were just formatted. Others were collected and summarised from discussions on AMD issue tracker[1][2]. [1] https://gitlab.freedesktop.org/drm/amd/-/issues/1734 [2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769 v2: - fix typos (Tales) - add MPCC to MPC entry in the glossary Signed-off-by: Melissa Wen Reviewed-by: Tales Aparecida Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

Documentation/amdgpu/display: add DC color caps info

2022-08-16T22:14:32Z

Add details about color correction capabilities and explain a bit about differences between DC hw generations and also how they are mapped between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted to svg from the original png) is included to illustrate it. They were obtained from a discussion[1] in the amd-gfx mailing list. [1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/ v1: - remove redundant comments (Harry) - fix typos (Harry) v2: - reword introduction of color section - add co-dev tag for Harry - who provided most of the info - fix typos (Tales) - describe missing struct parameters (Tales and Siqueira) Co-developed-by: Harry Wentland Signed-off-by: Harry Wentland Signed-off-by: Melissa Wen Reviewed-by: Tales Aparecida Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

Documentation/amdgpu_dm: Add DM color correction documentation

2022-08-16T22:14:32Z

AMDGPU DM maps DRM color management properties (degamma, ctm and gamma) to DC color correction entities. Part of this mapping is already documented as code comments and can be converted as kernel docs. v2: - rebase to amd-staging-drm-next - fix typos (Tales) - undo kernel-docs inside functions (Tales) Signed-off-by: Melissa Wen Reviewed-by: Harry Wentland Reviewed-by: Tales Aparecida Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

Documentation/gpu: Add GFXOFF section

2022-07-25T13:31:02Z

Add a GFXOFF section at "GPU Power Controls" file, explaining what it is and how userspace can interact with it. v2: minor tweaks to the documenation (Alex) Signed-off-by: André Almeida Signed-off-by: Alex Deucher

drm/amdgpu: Fix acronym typo in glossary

2022-07-13T15:25:18Z

The initialism of RunList Controller is RLC, not RCL Signed-off-by: Kent Russell Reviewed-by: Christian König Signed-off-by: Alex Deucher