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<title>user/sven/linux.git/Documentation, branch v5.3.3</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.3.3</id>
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<updated>2019-09-21T05:19:45Z</updated>
<entry>
<title>ovl: fix regression caused by overlapping layers detection</title>
<updated>2019-09-21T05:19:45Z</updated>
<author>
<name>Amir Goldstein</name>
<email>amir73il@gmail.com</email>
</author>
<published>2019-07-12T12:24:34Z</published>
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<id>urn:sha1:b66df96b7863a240a2247f920d103eac93f9c7c5</id>
<content type='text'>
commit 0be0bfd2de9dfdd2098a9c5b14bdd8f739c9165d upstream.

Once upon a time, commit 2cac0c00a6cd ("ovl: get exclusive ownership on
upper/work dirs") in v4.13 added some sanity checks on overlayfs layers.
This change caused a docker regression. The root cause was mount leaks
by docker, which as far as I know, still exist.

To mitigate the regression, commit 85fdee1eef1a ("ovl: fix regression
caused by exclusive upper/work dir protection") in v4.14 turned the
mount errors into warnings for the default index=off configuration.

Recently, commit 146d62e5a586 ("ovl: detect overlapping layers") in
v5.2, re-introduced exclusive upper/work dir checks regardless of
index=off configuration.

This changes the status quo and mount leak related bug reports have
started to re-surface. Restore the status quo to fix the regressions.
To clarify, index=off does NOT relax overlapping layers check for this
ovelayfs mount. index=off only relaxes exclusive upper/work dir checks
with another overlayfs mount.

To cover the part of overlapping layers detection that used the
exclusive upper/work dir checks to detect overlap with self upper/work
dir, add a trap also on the work base dir.

Link: https://github.com/moby/moby/issues/34672
Link: https://lore.kernel.org/linux-fsdevel/20171006121405.GA32700@veci.piliscsaba.szeredi.hu/
Link: https://github.com/containers/libpod/issues/3540
Fixes: 146d62e5a586 ("ovl: detect overlapping layers")
Cc: &lt;stable@vger.kernel.org&gt; # v4.19+
Signed-off-by: Amir Goldstein &lt;amir73il@gmail.com&gt;
Tested-by: Colin Walters &lt;walters@verbum.org&gt;
Signed-off-by: Miklos Szeredi &lt;mszeredi@redhat.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>Documentation: sphinx: Add missing comma to list of strings</title>
<updated>2019-09-21T05:19:42Z</updated>
<author>
<name>Jonathan Neuschäfer</name>
<email>j.neuschaefer@gmx.net</email>
</author>
<published>2019-08-12T16:07:04Z</published>
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<id>urn:sha1:9695dcbc8868d6a0695e232bfb7d9365ee5ad740</id>
<content type='text'>
commit 11fec009d97e5bd2329ef7d52d71e9f6763f1048 upstream.

In Python, like in C, when a comma is omitted in a list of strings, the
two strings around the missing comma are concatenated.

Cc: stable@vger.kernel.org  # v5.2 only
Signed-off-by: Jonathan Neuschäfer &lt;j.neuschaefer@gmx.net&gt;
Reviewed-by: Mauro Carvalho Chehab &lt;mchehab+samsung@kernel.org&gt;
Signed-off-by: Jonathan Corbet &lt;corbet@lwn.net&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>riscv: modify the Image header to improve compatibility with the ARM64 header</title>
<updated>2019-09-14T02:03:52Z</updated>
<author>
<name>Paul Walmsley</name>
<email>paul.walmsley@sifive.com</email>
</author>
<published>2019-09-14T01:35:50Z</published>
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<id>urn:sha1:474efecb65dceb15f793b6e2f2b226e952f0f8e9</id>
<content type='text'>
Part of the intention during the definition of the RISC-V kernel image
header was to lay the groundwork for a future merge with the ARM64
image header.  One error during my original review was not noticing
that the RISC-V header's "magic" field was at a different size and
position than the ARM64's "magic" field.  If the existing ARM64 Image
header parsing code were to attempt to parse an existing RISC-V kernel
image header format, it would see a magic number 0.  This is
undesirable, since it's our intention to align as closely as possible
with the ARM64 header format.  Another problem was that the original
"res3" field was not being initialized correctly to zero.

Address these issues by creating a 32-bit "magic2" field in the RISC-V
header which matches the ARM64 "magic" field.  RISC-V binaries will
store "RSC\x05" in this field.  The intention is that the use of the
existing 64-bit "magic" field in the RISC-V header will be deprecated
over time.  Increment the minor version number of the file format to
indicate this change, and update the documentation accordingly.  Fix
the assembler directives in head.S to ensure that reserved fields are
properly zero-initialized.

Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Reported-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Reviewed-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Cc: Atish Patra &lt;atish.patra@wdc.com&gt;
Cc: Karsten Merker &lt;merker@debian.org&gt;
Link: https://lore.kernel.org/linux-riscv/194c2f10c9806720623430dbf0cc59a965e50448.camel@wdc.com/T/#u
Link: https://lore.kernel.org/linux-riscv/mhng-755b14c4-8f35-4079-a7ff-e421fd1b02bc@palmer-si-x1e/T/#t</content>
</entry>
<entry>
<title>Documentation/process: Add Qualcomm process ambassador for hardware security issues</title>
<updated>2019-09-07T17:30:54Z</updated>
<author>
<name>Trilok Soni</name>
<email>tsoni@codeaurora.org</email>
</author>
<published>2019-09-06T19:01:57Z</published>
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<id>urn:sha1:a8e0abae2fe0e788fa3d92c043605d1211c13735</id>
<content type='text'>
Add Trilok Soni as process ambassador for hardware security issues
from Qualcomm.

Signed-off-by: Trilok Soni &lt;tsoni@codeaurora.org&gt;
Link: https://lore.kernel.org/r/1567796517-8964-1-git-send-email-tsoni@codeaurora.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Documentation/process/embargoed-hardware-issues: Microsoft ambassador</title>
<updated>2019-09-06T10:11:09Z</updated>
<author>
<name>Sasha Levin</name>
<email>sashal@kernel.org</email>
</author>
<published>2019-09-06T09:58:52Z</published>
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<id>urn:sha1:1f493162b59b09224de4d9c94e4392807e0edcce</id>
<content type='text'>
Add Sasha Levin as Microsoft's process ambassador.

Signed-off-by: Sasha Levin &lt;alexander.levin@microsoft.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
Link: https://lore.kernel.org/r/20190906095852.23568-1-sashal@kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Documentation/process: Add Google contact for embargoed hardware issues</title>
<updated>2019-09-05T05:43:34Z</updated>
<author>
<name>Kees Cook</name>
<email>keescook@chromium.org</email>
</author>
<published>2019-09-04T16:24:49Z</published>
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<id>urn:sha1:f56f791f6d8e8296c9dd194506ee2b703b1227d4</id>
<content type='text'>
This adds myself as the Google contact for embargoed hardware security
issues and fixes some small typos.

Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Matt Linton &lt;amuse@google.com&gt;
Cc: Matthew Garrett &lt;mjg59@google.com&gt;
Signed-off-by: Kees Cook &lt;keescook@chromium.org&gt;
Acked-by: Guenter Roeck &lt;groeck@chromium.org&gt;
Link: https://lore.kernel.org/r/201909040922.56496BF70@keescook
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Documentation/process: Volunteer as the ambassador for Xen</title>
<updated>2019-09-05T05:43:30Z</updated>
<author>
<name>Andrew Cooper</name>
<email>andrew.cooper3@citrix.com</email>
</author>
<published>2019-09-04T18:17:02Z</published>
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<id>urn:sha1:02e740aeca79e9a3c464bc2ebb510457c85d2015</id>
<content type='text'>
Cc: Jonathan Corbet &lt;corbet@lwn.net&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Tyler Hicks &lt;tyhicks@canonical.com&gt;
Cc: Ben Hutchings &lt;ben@decadent.org.uk&gt;
Cc: Konrad Rzeszutek Wilk &lt;konrad.wilk@oracle.com&gt;
Cc: Josh Poimboeuf &lt;jpoimboe@redhat.com&gt;
Cc: Jiri Kosina &lt;jkosina@suse.cz&gt;
Signed-off-by: Andrew Cooper &lt;andrew.cooper3@citrix.com&gt;
Link: https://lore.kernel.org/r/20190904181702.19788-1-andrew.cooper3@citrix.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'char-misc-5.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc</title>
<updated>2019-09-02T16:30:34Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-09-02T16:30:34Z</published>
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<id>urn:sha1:49ffdb4c7c65082cee24a53a7ebd62e00eb2e9e9</id>
<content type='text'>
Pull char/misc driver fixes from Greg KH:
 "Here are some small char and misc driver fixes for reported issues for
  5.3-rc7

  Also included in here is the documentation for how we are handling
  hardware issues under embargo that everyone has finally agreed on, as
  well as a MAINTAINERS update for the suckers who agreed to handle the
  LICENSES/ files.

  All of these have been in linux-next last week with no reported
  issues"

* tag 'char-misc-5.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
  fsi: scom: Don't abort operations for minor errors
  vmw_balloon: Fix offline page marking with compaction
  VMCI: Release resource if the work is already queued
  Documentation/process: Embargoed hardware security issues
  lkdtm/bugs: fix build error in lkdtm_EXHAUST_STACK
  mei: me: add Tiger Lake point LP device ID
  intel_th: pci: Add Tiger Lake support
  intel_th: pci: Add support for another Lewisburg PCH
  stm class: Fix a double free of stm_source_device
  MAINTAINERS: add entry for LICENSES and SPDX stuff
  fpga: altera-ps-spi: Fix getting of optional confd gpio
</content>
</entry>
<entry>
<title>dt-bindings: net: dsa: document additional Microchip KSZ8563 switch</title>
<updated>2019-09-01T06:36:37Z</updated>
<author>
<name>Razvan Stefanescu</name>
<email>razvan.stefanescu@microchip.com</email>
</author>
<published>2019-08-30T07:52:01Z</published>
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<id>urn:sha1:de5eb9e00eba00783f49da37377bd2a93d38fe42</id>
<content type='text'>
It is a 3-Port 10/100 Ethernet Switch with 1588v2 PTP.

Signed-off-by: Razvan Stefanescu &lt;razvan.stefanescu@microchip.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>macb: bindings doc: update sifive fu540-c000 binding</title>
<updated>2019-08-28T21:05:48Z</updated>
<author>
<name>Yash Shah</name>
<email>yash.shah@sifive.com</email>
</author>
<published>2019-08-27T05:06:03Z</published>
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<id>urn:sha1:abecec415dc2b5a5d11fe1b17963564b13f2ff20</id>
<content type='text'>
As per the discussion with Nicolas Ferre[0], rename the compatible property
to a more appropriate and specific string.

[0] https://lore.kernel.org/netdev/CAJ2_jOFEVZQat0Yprg4hem4jRrqkB72FKSeQj4p8P5KA-+rgww@mail.gmail.com/

Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Acked-by: Nicolas Ferre &lt;nicolas.ferre@microchip.com&gt;
Reviewed-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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