user/sven/linux.git/arch/mips/include/asm/bitops.h, branch v3.3.4

bitops: remove minix bitops from asm/bitops.h

2011-03-24T02:46:22Z

minix bit operations are only used by minix filesystem and useless by other modules. Because byte order of inode and block bitmaps is different on each architecture like below: m68k: big-endian 16bit indexed bitmaps h8300, microblaze, s390, sparc, m68knommu: big-endian 32 or 64bit indexed bitmaps m32r, mips, sh, xtensa: big-endian 32 or 64bit indexed bitmaps for big-endian mode little-endian bitmaps for little-endian mode Others: little-endian bitmaps In order to move minix bit operations from asm/bitops.h to architecture independent code in minix filesystem, this provides two config options. CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED is only selected by m68k. CONFIG_MINIX_FS_NATIVE_ENDIAN is selected by the architectures which use native byte order bitmaps (h8300, microblaze, s390, sparc, m68knommu, m32r, mips, sh, xtensa). The architectures which always use little-endian bitmaps do not select these options. Finally, we can remove minix bit operations from asm/bitops.h for all architectures. Signed-off-by: Akinobu Mita Acked-by: Arnd Bergmann Acked-by: Greg Ungerer Cc: Geert Uytterhoeven Cc: Roman Zippel Cc: Andreas Schwab Cc: Martin Schwidefsky Cc: Heiko Carstens Cc: Yoshinori Sato Cc: Michal Simek Cc: "David S. Miller" Cc: Hirokazu Takata Acked-by: Ralf Baechle Acked-by: Paul Mundt Cc: Chris Zankel Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

bitops: remove ext2 non-atomic bitops from asm/bitops.h

2011-03-24T02:46:21Z

As the result of conversions, there are no users of ext2 non-atomic bit operations except for ext2 filesystem itself. Now we can put them into architecture independent code in ext2 filesystem, and remove from asm/bitops.h for all architectures. Signed-off-by: Akinobu Mita Cc: Jan Kara Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

bitops: introduce little-endian bitops for most architectures

2011-03-24T02:46:15Z

Introduce little-endian bit operations to the big-endian architectures which do not have native little-endian bit operations and the little-endian architectures. (alpha, avr32, blackfin, cris, frv, h8300, ia64, m32r, mips, mn10300, parisc, sh, sparc, tile, x86, xtensa) These architectures can just include generic implementation (asm-generic/bitops/le.h). Signed-off-by: Akinobu Mita Cc: Richard Henderson Cc: Ivan Kokshaysky Cc: Mikael Starvik Cc: David Howells Cc: Yoshinori Sato Cc: "Luck, Tony" Cc: Ralf Baechle Cc: Kyle McMartin Cc: Matthew Wilcox Cc: Grant Grundler Cc: Paul Mundt Cc: Kazumoto Kojima Cc: Hirokazu Takata Cc: "David S. Miller" Cc: Chris Zankel Cc: Ingo Molnar Cc: Thomas Gleixner Acked-by: Hans-Christian Egtvedt Acked-by: "H. Peter Anvin" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

MIPS: Get rid of branches to .subsections.

2010-10-29T18:08:24Z

It was a nice optimization - on paper at least. In practice it results in branches that may exceed the maximum legal range for a branch. We can fight that problem with -ffunction-sections but -ffunction-sections again is incompatible with -pg used by the function tracer. By rewriting the loop around all simple LL/SC blocks to C we reduce the amount of inline assembler and at the same time allow GCC to often fill the branch delay slots with something sensible or whatever else clever optimization it may have up in its sleeve. With this optimization gone we also no longer need -ffunction-sections, so drop it. This optimization was originally introduced in 2.6.21, commit 5999eca25c1fd4b9b9aca7833b04d10fe4bc877d (linux-mips.org) rsp. f65e4fa8e0c6022ad58dc88d1b11b12589ed7f9f (kernel.org). Original fix for the issues which caused me to pull this optimization by Paul Gortmaker . Signed-off-by: Ralf Baechle

MIPS: Create and use asm/arch_hweight.h

2010-08-05T12:26:02Z

Some MIPS ISA processor varients can do hweight operations efficiently. Split arch_hweight.h into a seperate file, and implement the operations with __builtin_popcount{,ll} if supported. Signed-off-by: David Daney To: linux-mips@linux-mips.org Cc: David Daney Patchwork: https://patchwork.linux-mips.org/patch/1430/ Signed-off-by: Ralf Baechle

MIPS: New macro smp_mb__before_llsc.

2010-02-27T11:53:06Z

Replace some instances of smp_llsc_mb() with a new macro smp_mb__before_llsc(). It is used before ll/sc sequences that are documented as needing write barrier semantics. The default implementation of smp_mb__before_llsc() is just smp_llsc_mb(), so there are no changes in semantics. Also simplify definition of smp_mb(), smp_rmb(), and smp_wmb() to be just barrier() in the non-SMP case. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/851/ Signed-off-by: Ralf Baechle

MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.

2009-09-17T18:07:50Z

On some CPUs, it is more efficient to disable and enable interrupts in the kernel rather than use ll/sc for atomic operations. But if we were to set cpu_has_llsc to false, we would break the userspace futex interface (in asm/futex.h). We separate the two concepts, with a new predicate kernel_uses_llsc, that lets us disable the kernel's use of ll/sc while still allowing the futex code to use it. Also there were a couple of cases in bitops.h where we were using ll/sc unconditionally even if cpu_has_llsc were false. Signed-off-by: David Daney Signed-off-by: Ralf Baechle

MIPS: Enable CLO / CLZ instructions via separate CPU property

2009-05-14T12:50:26Z

This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do not implement the full MIPS32 / MIPS64 architecture. Signed-off-by: Ralf Baechle

MIPS: Clean up MIPSxx-optimized bitop functions

2008-10-30T14:44:33Z

Signed-off-by: Ralf Baechle

MIPS: Move headfiles to new location below arch/mips/include

2008-10-11T15:18:52Z

Signed-off-by: Ralf Baechle