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<title>user/sven/linux.git/arch/mips/lib/Makefile, branch v4.4.4</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2015-10-26T08:49:43Z</updated>
<entry>
<title>MIPS: Use ARCH_USE_BUILTIN_BSWAP.</title>
<updated>2015-10-26T08:49:43Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2015-09-29T10:19:48Z</published>
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<id>urn:sha1:1ee3630a3e57f38f688a6f0a5f9edbd8a0d7201f</id>
<content type='text'>
ARCH_USE_BUILTIN_BSWAP will use __builtin_bswap16(), __builtin_bswap32()
and __builtin_bswap64() where available.  This allows better instruction
scheduling.  On pre-R2 processors it will result in 32 bit and 64 bit
swapping being performed in a call to a __bswapsi2() rsp. __bswapdi2()
functions, so we add these, too.

For a 4.2 kernel with GCC 4.9 this yields the following kernel sizes:

   text    data     bss     dec     hex filename
3996071  155804   88992 4240867  40b5e3 vmlinux         ip22 baseline
3985687  159900   88992 4234579  409d53 vmlinux         ip22 + bswap patch
6913157  378552  251024 7542733  7317cd vmlinux         ip27 baseline
6878581  378552  251024 7508157  7290bd vmlinux         ip27 + bswap patch
5773777  268752  187424 6229953  5f0fc1 vmlinux         malta baseline
5773401  268752  187424 6229577  5f0e49 vmlinux         malta + bswap patch

Presumably the code size improvments yield better cache hit rate thus
better performance compensating for the extra function call but this
will still need to be benchmarked.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Use generic checksum functions for MIPS R6</title>
<updated>2015-02-17T15:37:19Z</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2014-11-13T11:25:27Z</published>
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<id>urn:sha1:4e0748f5beb92a14f6be4716938cbf27177ecd07</id>
<content type='text'>
The following instructions have been removed from MIPS R6

ulw, ulh, swl, lwr, lwl, swr.

However, all of them are used in the MIPS specific checksum implementation.
As a result of which, we will use the generic checksum on MIPS R6

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
</content>
</entry>
<entry>
<title>MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus</title>
<updated>2012-11-09T09:59:21Z</updated>
<author>
<name>Jim Quinlan</name>
<email>jim2101024@gmail.com</email>
</author>
<published>2012-09-06T15:36:56Z</published>
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<id>urn:sha1:e97c5b609880d97313b13eb71830fca62cee50c2</id>
<content type='text'>
For non MIPSr2 processors, such as the BMIPS 5000, calls to
arch_local_irq_disable() and others may be preempted, and in doing
so a stale value may be restored to c0_status.  This fix disables
preemption for such processors prior to the call and enables it
after the call.

Those functions that needed this fix have been "outlined" to
mips-atomic.c, as they are no longer good candidates for inlining.

This bug was observed in a BMIPS 5000, occuring once every few hours
in a continuous reboot test.  It was traced to the write_lock_irq()
function which was being invoked in release_task() in exit.c.
By placing a number of "nops" inbetween the mfc0/mtc0 pair in
arch_local_irq_disable(), which is called by write_lock_irq(), we
were able to greatly increase the occurance of this bug.  Similarly,
the application of this commit silenced the bug.

Signed-off-by: Jim Quinlan &lt;jim2101024@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Cc: David Daney &lt;ddaney.cavm@gmail.com&gt;
Cc: Kevin Cernekee cernekee@gmail.com
Cc: Jim Quinlan &lt;jim2101024@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/4321/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Remove irqflags.h dependency from bitops.h</title>
<updated>2012-11-09T09:59:10Z</updated>
<author>
<name>Jim Quinlan</name>
<email>jim2101024@gmail.com</email>
</author>
<published>2012-09-06T15:36:55Z</published>
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<id>urn:sha1:92d11594f688c8b55b51e80f2eac4417396237a4</id>
<content type='text'>
The "else clause" of most functions in bitops.h invoked
raw_local_irq_{save,restore}() and in doing so had a dependency on
irqflags.h.  This fix moves said code to bitops.c, removing the
dependency.

Signed-off-by: Jim Quinlan &lt;jim2101024@gmail.com&gt;
Cc: linux-mips@linux-mips.org
Cc: David Daney &lt;ddaney.cavm@gmail.com&gt;
Cc: Kevin Cernekee cernekee@gmail.com
Cc: Jim Quinlan &lt;jim2101024@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/4320/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: introduce CPU_GENERIC_DUMP_TLB</title>
<updated>2012-08-22T21:46:38Z</updated>
<author>
<name>Florian Fainelli</name>
<email>florian@openwrt.org</email>
</author>
<published>2012-01-31T17:18:43Z</published>
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<id>urn:sha1:3165c846a2aa7ce25d5f1db6be9960ebeeb9bb0b</id>
<content type='text'>
Allows us not to duplicate more lines in arch/mips/lib/Makefile.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Patchwork: http://patchwork.linux-mips.org/patch/3329/
Signed-off-by: John Crispin &lt;blogic@openwrt.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Unify memcpy.S and memcpy-inatomic.S</title>
<updated>2012-07-23T12:55:55Z</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2012-06-06T22:00:31Z</published>
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<id>urn:sha1:bb0757ebb929d5d6ba484b4313976847285ba280</id>
<content type='text'>
We can save the 451 lines of code that comprise memcpy-inatomic.S at the
expense of a single instruction in the memcpy prolog.  We also use an
additional register (t6), so this may cause increased register pressure in
some places as well.  But I think the reduced maintenance burden, of not
having two nearly identical implementations, makes it worth it.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Netlogic: Add XLP makefiles and config</title>
<updated>2011-12-07T22:04:56Z</updated>
<author>
<name>Jayachandran C</name>
<email>jayachandranc@netlogicmicro.com</email>
</author>
<published>2011-11-16T00:21:28Z</published>
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<id>urn:sha1:1c773ea4dceff889c2f872343609a87ae0cfbf56</id>
<content type='text'>
- Add CPU_XLP and NLM_XLR_BOARD to arch/mips/Kconfig for Netlogic XLP boards
- Update mips Makefiles to add XLP

Signed-off-by: Jayachandran C &lt;jayachandranc@netlogicmicro.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2968/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Kconfig and Makefile update for Netlogic XLR/XLS</title>
<updated>2011-05-19T08:55:40Z</updated>
<author>
<name>Jayachandran C</name>
<email>jayachandranc@netlogicmicro.com</email>
</author>
<published>2011-05-06T20:06:57Z</published>
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<id>urn:sha1:7f058e852b229ec77b37676b2b78baf2e78ffee8</id>
<content type='text'>
Add NLM_XLR_BOARD, CPU_XLR and other config options
Makefile updates, mostly based on r4k

Signed-off-by: Jayachandran C &lt;jayachandranc@netlogicmicro.com&gt;
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2334/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Outline udelay and fix a few issues.</title>
<updated>2009-06-08T15:57:51Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2009-02-28T09:44:28Z</published>
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<id>urn:sha1:5636919b5c909fee54a6ef5226475ecae012ad02</id>
<content type='text'>
Outlining fixes the issue were on certain CPUs such as the R10000 family
the delay loop would need an extra cycle if it overlaps a cacheline
boundary.

The rewrite also fixes build errors with GCC 4.4 which was changed in
way incompatible with the kernel's inline assembly.

Relying on pure C for computation of the delay value removes the need for
explicit.  The price we pay is a slight slowdown of the computation - to
be fixed on another day.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Hook up Cavium OCTEON in arch/mips.</title>
<updated>2009-01-11T09:57:22Z</updated>
<author>
<name>David Daney</name>
<email>ddaney@caviumnetworks.com</email>
</author>
<published>2008-12-11T23:33:28Z</published>
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<id>urn:sha1:7e69deb83c9fffe75e8ea17fb40a63375e56ac9f</id>
<content type='text'>
Take all the OCTEON specific files that were added, and hook them into
the build system for the arch/mips.  For versions of GCC that lack
OCTEON support, override gas target architecture.

Signed-off-by: Tomaso Paoletti &lt;tpaoletti@caviumnetworks.com&gt;
Signed-off-by: David Daney &lt;ddaney@caviumnetworks.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
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