user/sven/linux.git/arch/powerpc/kernel/cpu_setup_power.S, branch v4.4.27

powerpc/book3s: Fix flush_tlb cpu_spec hook to take a generic argument.

2015-03-16T20:52:48Z

The flush_tlb hook in cpu_spec was introduced as a generic function hook to invalidate TLBs. But the current implementation of flush_tlb hook takes IS (invalidation selector) as an argument which is architecture dependent. Hence, It is not right to have a generic routine where caller has to pass non-generic argument. This patch fixes this and makes flush_tlb hook as high level API. Reported-by: Benjamin Herrenschmidt Signed-off-by: Mahesh Salgaonkar Signed-off-by: Michael Ellerman

powerpc/powernv: Enable POWER8 doorbell IPIs

2014-06-11T07:05:12Z

This patch enables POWER8 doorbell IPIs on powernv. Since doorbells can only IPI within a core, we test to see when we can use doorbells and if not we fall back to XICS. This also enables hypervisor doorbells to wakeup us up from nap/sleep via the LPCR PECEDH bit. Based on tests by Anton, the best case IPI latency between two threads dropped from 894ns to 512ns. Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt

powerpc/ppc64: Do not turn AIL (reloc-on interrupts) too early

2014-04-07T00:33:15Z

Turn them on at the same time as we allow MSR_IR/DR in the paca kernel MSR, ie, after the MMU has been setup enough to be able to handle relocated access to the linear mapping. Signed-off-by: Benjamin Herrenschmidt

powerpc/book3s: Add flush_tlb operation in cpu_spec.

2013-12-05T05:04:38Z

This patch introduces flush_tlb operation in cpu_spec structure. This will help us to invoke appropriate CPU-side flush tlb routine. This patch adds the foundation to invoke CPU specific flush routine for respective architectures. Currently this patch introduce flush_tlb for p7 and p8. Signed-off-by: Mahesh Salgaonkar Acked-by: Paul Mackerras Signed-off-by: Benjamin Herrenschmidt

powerpc: Fix TLB cleanup at boot on POWER8

2013-05-24T08:13:44Z

The TLB has 512 congruence classes (2048 entries 4 way set associative) while P7 had 128 Signed-off-by: Benjamin Herrenschmidt

powerpc: Turn on the EBB H/FSCR bits

2013-05-02T00:36:55Z

This turns Event Based Branching (EBB) on in the Hypervisor Facility Status and Control Register (HFSCR) and Facility Status and Control Register (FSCR). Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt

powerpc: Setup BHRB instructions facility in HFSCR for POWER8

2013-05-02T00:35:15Z

Make BHRB instructions available in problem and privileged states. Signed-off-by: Anshuman Khandual Signed-off-by: Benjamin Herrenschmidt

powerpc: Initialise PMU related regs on Power8

2013-04-26T06:11:06Z

For both HV and guest kernels, intialise PMU regs to something sane. Signed-off-by: Michael Ellerman Acked-by: Paul Mackerras Signed-off-by: Benjamin Herrenschmidt

powerpc/power8: Fix secondary CPUs hanging on boot for HV=0

2013-04-26T06:08:17Z

In __restore_cpu_power8 we determine if we are HV and if not, we return before setting HV only resources. Unfortunately we forgot to restore the link register from r11 before returning. This will happen on boot and with secondary CPUs not coming online. This adds the missing link register restore. Signed-off-by: Michael Neuling CC: Signed-off-by: Benjamin Herrenschmidt

powerpc: Setup in HFSCR for POWER8

2013-04-18T03:03:59Z

Setup the HFSCR (Hypervisor Facility Status and Control Register) for POWER8 when running HV=1. The HFSCR is the same as the FSCR except it's for hypervisors. It controls the available of various facilities in OS and userspace levels. It also indicates the cause of a hypervisor facility unavailable interrupt (although we are not using this here). This patch sets the facilities Linux knows about incase the firmware doesn't. Signed-off-by: Michael Neuling Signed-off-by: Michael Ellerman