user/sven/linux.git/drivers/Makefile, branch v6.7.9

Merge tag 'mips_6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2023-11-10T17:19:46Z

Pull MIPS updates from Thomas Bogendoerfer: - removed AR7 platform support - cleanups and fixes * tag 'mips_6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: AR7: remove platform watchdog: ar7_wdt: remove driver to prepare for platform removal vlynq: remove bus driver mtd: parsers: ar7: remove support serial: 8250: remove AR7 support arch: mips: remove ReiserFS from defconfig MIPS: lantiq: Remove unnecessary include of MIPS: lantiq: Fix pcibios_plat_dev_init() "no previous prototype" warning MIPS: KVM: Fix a build warning about variable set but not used MIPS: Remove dead code in relocate_new_kernel mips: dts: ralink: mt7621: rename to GnuBee GB-PC1 and GnuBee GB-PC2 mips: dts: ralink: mt7621: define each reset as an item mips: dts: ingenic: Remove unneeded probe-type properties MIPS: loongson32: Remove dma.h and nand.h

vlynq: remove bus driver

2023-10-19T08:33:10Z

There are no users with a vlynq_driver in the Kernel tree. Also, only the AR7 platform ever initialized a VLYNQ bus, but AR7 is going to be removed from the Kernel. OpenWRT had some out-of-tree drivers which they probably intended to upport, but AR7 devices are even there not supported anymore because they are "stuck with Kernel 3.18" [1]. This code can go. [1] https://openwrt.org/docs/techref/targets/ar7 Signed-off-by: Wolfram Sang Acked-by: Greg Kroah-Hartman Acked-by: Florian Fainelli Signed-off-by: Thomas Bogendoerfer

dpll: core: Add DPLL framework base functions

2023-09-17T10:50:20Z

DPLL framework is used to represent and configure DPLL devices in systems. Each device that has DPLL and can configure inputs and outputs can use this framework. Implement core framework functions for further interactions with device drivers implementing dpll subsystem, as well as for interactions of DPLL netlink framework part with the subsystem itself. Co-developed-by: Milena Olech Signed-off-by: Milena Olech Co-developed-by: Michal Michalik Signed-off-by: Michal Michalik Signed-off-by: Vadim Fedorenko Co-developed-by: Arkadiusz Kubalewski Signed-off-by: Arkadiusz Kubalewski Signed-off-by: Jiri Pirko Signed-off-by: David S. Miller

pmdomain: Rename the genpd subsystem to pmdomain

2023-09-13T09:09:21Z

It has been pointed out that naming a subsystem "genpd" isn't very self-explanatory and the acronym itself that means Generic PM Domain, is known only by a limited group of people. In a way to improve the situation, let's rename the subsystem to pmdomain, which ideally should indicate that this is about so called Power Domains or "PM domains" as we often also use within the Linux Kernel terminology. Suggested-by: Rafael J. Wysocki Signed-off-by: Ulf Hansson Reviewed-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Heiko Stuebner Acked-by: Rafael J. Wysocki Acked-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230912221127.487327-1-ulf.hansson@linaro.org

Merge patch series "Add non-coherent DMA support for AX45MP"

2023-09-08T18:24:34Z

Prabhakar says: From: Lad Prabhakar non-coherent DMA support for AX45MP ==================================== On the Andes AX45MP core, cache coherency is a specification option so it may not be supported. In this case DMA will fail. To get around with this issue this patch series does the below: 1] Andes alternative ports is implemented as errata which checks if the IOCP is missing and only then applies to CMO errata. One vendor specific SBI EXT (ANDES_SBI_EXT_IOCP_SW_WORKAROUND) is implemented as part of errata. Below are the configs which Andes port provides (and are selected by RZ/Five): - ERRATA_ANDES - ERRATA_ANDES_CMO OpenSBI patch supporting ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI is now part v1.3 release. 2] Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. OpenSBI configures the PMA regions as required and creates a reserve memory node and propagates it to the higher boot stack. Currently OpenSBI (upstream) configures the required PMA region and passes this a shared DMA pool to Linux. reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; The above shared DMA pool gets appended to Linux DTB so the DMA memory requests go through this region. 3] We provide callbacks to synchronize specific content between memory and cache. 4] RZ/Five SoC selects the below configs - AX45MP_L2_CACHE - DMA_GLOBAL_POOL - ERRATA_ANDES - ERRATA_ANDES_CMO ----------x---------------------x--------------------x---------------x---- * b4-shazam-merge: soc: renesas: Kconfig: Select the required configs for RZ/Five SoC cache: Add L2 cache management for Andes AX45MP RISC-V core dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller riscv: mm: dma-noncoherent: nonstandard cache operations support riscv: errata: Add Andes alternative ports riscv: asm: vendorid_list: Add Andes Technology to the vendors list Link: https://lore.kernel.org/r/20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt

cache: Add L2 cache management for Andes AX45MP RISC-V core

2023-09-01T16:08:59Z

I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passes as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Tested-by: Conor Dooley # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt

Merge tag 'genpd-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm

2023-08-30T23:37:00Z

Pull ARM SoC generic power domain driver updates from Ulf Hansson: "This adds a new subsystem for generic power domain providers in drivers/genpd and starts moving some of the corresponding code in there. We have currently ~60 users of the genpd provider interface, which are sprinkled across various subsystems. To release some burden from the soc maintainers (Arnd Bergmann, etc) in particular, but also to gain a better overall view of what goes on in the area, I will help out with maintenance" [ I find the "genpd" name singularly uninformative, so we'll probably end up moving this driver subsystem somewhere else, but that's still being discussed - Linus ] * tag 'genpd-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (30 commits) genpd: ti: Use for_each_node_with_property() simplify code logic genpd: Explicitly include correct DT includes genpd: imx: scu-pd: initialize is_off according to HW state genpd: imx: scu-pd: Suppress bind attrs genpd: imx: scu-pd: do not power off console if no_console_suspend genpd: imx: scu-pd: add more PDs genpd: imx: scu-pd: enlarge PD range genpd: imx: relocate scu-pd under genpd MAINTAINERS: adjust file entry in STARFIVE JH71XX PMU CONTROLLER DRIVER genpd: Makefile: build imx genpd: move owl-sps-helper.c from drivers/soc soc: starfive: remove stale Makefile entry ARM: ux500: Move power-domain driver to the genpd dir ARM: ux500: Convert power-domain code into a regular platform driver soc: xilinx: Move power-domain driver to the genpd dir soc: ti: Mover power-domain drivers to the genpd dir soc: tegra: Move powergate-bpmp driver to the genpd dir soc: sunxi: Move power-domain driver to the genpd dir soc: starfive: Move the power-domain driver to the genpd dir soc: samsung: Move power-domain driver to the genpd dir ...

s390: use obj-y to descend into drivers/s390/

2023-07-24T10:12:25Z

The single build rule does not work with the drivers-y syntax. [1] Use the standard obj-y syntax. It moves the objects from drivers/s390/ to slightly lower address, but fixes the reported issue. [1]: https://lore.kernel.org/linux-kbuild/d57ba55f-20a3-b836-783d-b49c8a161b6e@kernel.org/T/#m27f781ab60acadfed8a9e9642f30d5414a5e2df3 Signed-off-by: Masahiro Yamada Tested-by: Jiri Slaby Link: https://lore.kernel.org/r/20230721171358.3612099-1-masahiroy@kernel.org Signed-off-by: Heiko Carstens

genpd: Create a new subsystem directory to host genpd providers

2023-07-11T13:29:38Z

There are currently ~60 users of the genpd provider interface, which implementations are sprinkled across various subsystems. To simplify with maintenance let's create a new subsystem (drivers/genpd) and start moving the providers in there. My intention is also to host a git tree to collect and to get the patches tested/integrated through the linux-next tree. Ideally this should release some of the burden on the soc maintainers. Note that, I will of course require acks/reviews from the current platform maintainers, hence the MAINTAINERS file needs to be updated accordingly for each genpd provider that is moved into the new genpd subsystem. Signed-off-by: Ulf Hansson

cdx: add the cdx bus driver

2023-03-29T10:26:32Z

Introduce AMD CDX bus, which provides a mechanism for scanning and probing CDX devices. These devices are memory mapped on system bus for Application Processors(APUs). CDX devices can be changed dynamically in the Fabric and CDX bus interacts with CDX controller to rescan the bus and rediscover the devices. Signed-off-by: Nipun Gupta Reviewed-by: Pieter Jansen van Vuuren Tested-by: Nikhil Agarwal Link: https://lore.kernel.org/r/20230313132636.31850-2-nipun.gupta@amd.com Signed-off-by: Greg Kroah-Hartman