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<title>user/sven/linux.git/drivers/cache/starfive_starlink_cache.c, branch v6.12.22</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v6.12.22</id>
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<updated>2024-05-28T11:34:11Z</updated>
<entry>
<title>cache: Add StarFive StarLink cache management</title>
<updated>2024-05-28T11:34:11Z</updated>
<author>
<name>Joshua Yeong</name>
<email>joshua.yeong@starfivetech.com</email>
</author>
<published>2024-05-15T05:02:52Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=cabff60ca77da6cb460988e2af40bde95776d92b'/>
<id>urn:sha1:cabff60ca77da6cb460988e2af40bde95776d92b</id>
<content type='text'>
Add StarFive Starlink cache management driver.
The driver enables RISC-V non-standard cache
operation on SoC that does not support Zicbom
extension instructions.

Signed-off-by: Joshua Yeong &lt;joshua.yeong@starfivetech.com&gt;
Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
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