user/sven/linux.git/drivers/clk/ti, branch leds/master

Merge tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2015-07-02T02:22:00Z

Pull clock framework updates from Michael Turquette: "The changes to the common clock framework for 4.2 are dominated by new drivers and updates to existing ones, as usual. There are some fixes to the framework itself and several cleanups for sparse warnings, etc" * tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits) clk: stm32: Add clock driver for STM32F4[23]xxx devices dt-bindings: Document the STM32F4 clock bindings cpufreq: exynos: remove Exynos4210 specific cpufreq driver support ARM: Exynos: switch to using generic cpufreq driver for Exynos4210 clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock clk: samsung: add infrastructure to register cpu clocks clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support doc: dt: add documentation for lpc1850-ccu clk driver clk: add lpc18xx ccu clk driver doc: dt: add documentation for lpc1850-cgu clk driver clk: add lpc18xx cgu clk driver clk: keystone: add support for post divider register for main pll clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSED clk: cygnus: remove Cygnus dummy clock binding clk: cygnus: add clock support for Broadcom Cygnus clk: Change bcm clocks build dependency clk: iproc: add initial common clock support clk: iproc: define Broadcom iProc clock binding MAINTAINERS: update email for Michael Turquette clk: meson: add some error handling in meson_clk_register_cpu() ...

clk: ti: Use of_clk_get_parent_count() instead of open coding

2015-06-04T20:51:37Z

Signed-off-by: Geert Uytterhoeven Signed-off-by: Stephen Boyd

CLK: TI: always enable DESHDCP clock

2015-06-04T06:00:52Z

DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That clock is an odd one, as it is not supposed to be any kind of core clock for DSS, and we don't even support HDCP, but the clock is still needed even for the HWMOD framework to be able to reset the DSS IP. As there's no support for multiple core clocks in the HWMOD framework, we don't have any obvious place to enable this clock when DSS IP is being enabled. Furthermore, the HDMI on OMAP5 DSS is the same as on DRA7, and OMAP5 does not have any such clock configuration bit. This suggests that on OMAP5 the DESHDCP clock is always enabled, and for DRA7 we have the possibility to gate it. So, as we don't have any clean way to enable and disable the clock based on the need, this patch enables the clock at boot time, making it work similarly to OMAP5. Signed-off-by: Tomi Valkeinen Acked-by: Tero Kristo Acked-by: Michael Turquette

arm: dra7: add DESHDCP clock

2015-06-03T11:23:25Z

Add a new Linux clock for DRA7 based SoCs to control DESHDCP clock. Signed-off-by: Tomi Valkeinen Acked-by: Tero Kristo

clk: ti: Silence sparse warnings

2015-05-15T00:11:26Z

drivers/clk/ti/clk.c:125:31: warning: incorrect type in return expression (different address spaces) drivers/clk/ti/clk.c:125:31: expected void [noderef] * drivers/clk/ti/clk.c:125:31: got void * drivers/clk/ti/clk.c:132:31: warning: incorrect type in return expression (different address spaces) drivers/clk/ti/clk.c:132:31: expected void [noderef] * drivers/clk/ti/clk.c:132:31: got void * drivers/clk/ti/dpll.c:180:14: warning: symbol '_get_reg' was not declared. Should it be static? drivers/clk/ti/fapll.c:624:32: warning: Using plain integer as NULL pointer drivers/clk/ti/fapll.c:625:31: warning: Using plain integer as NULL pointer drivers/clk/ti/fapll.c:630:40: warning: Using plain integer as NULL pointer drivers/clk/ti/clk-dra7-atl.c:158:22: warning: symbol 'atl_clk_ops' was not declared. Should it be static? drivers/clk/ti/clk-dra7-atl.c:170:39: warning: Using plain integer as NULL pointer Acked-by: Peter Ujfalusi Acked-by: Tero Kristo Signed-off-by: Stephen Boyd

clk: ti: dra7-atl-clock: Fix possible ERR_PTR dereference

2015-05-14T21:04:18Z

of_clk_get_from_provider() returns ERR_PTR on failure. The dra7-atl-clock driver was not checking its return value and immediately used it in __clk_get_hw(). __clk_get_hw() dereferences supplied clock, if it is not NULL, so in that case it would dereference an ERR_PTR. Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd

clk: don't use __initconst for non-const arrays

2015-04-13T00:18:27Z

The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König Signed-off-by: Michael Turquette

clk: constify of_device_id array

2015-04-01T17:59:27Z

of_device_id is always used as const. (See driver.of_match_table and open firmware functions) __initdata updated to __initconst for static const struct of_device_id ti_clkdm_match_table[] Signed-off-by: Fabian Frederick Signed-off-by: Stephen Boyd

Merge branch 'for-4.1-clk-ti' of github.com:t-kristo/linux-pm into clk-next

2015-03-24T23:47:43Z

clk: ti: Implement FAPLL set_rate for the PLL

2015-03-24T18:26:14Z

Since we have a fractional divider for the synthesizer, just implement a simple multiply logic for the PLL. It seems the PLL divider needs to have also the multiplier set for the PLL to lock. At least I have not yet figured out if divided rates are doable. So let's just ignore the PLL divider for now as the synthesizer has both integer and fractional dividers so we don't even need to use the PLL divider for the rates we know work with PLL locking. Cc: Brian Hutchinson Cc: Matthijs van Duin Cc: Tero Kristo Signed-off-by: Tony Lindgren Signed-off-by: Tero Kristo