user/sven/linux.git/drivers/clocksource/timer-sp804.c, branch v5.10.167

clocksource/drivers/sp804: Avoid error on multiple instances

2022-06-14T16:32:43Z

[ Upstream commit a98399cbc1e05f7b977419f03905501d566cf54e ] When a machine sports more than one SP804 timer instance, we only bring up the first one, since multiple timers of the same kind are not useful to Linux. As this is intentional behaviour, we should not return an error message, as we do today: =============== [ 0.000800] Failed to initialize '/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/timer@120000': -22 =============== Replace the -EINVAL return with a debug message and return 0 instead. Also we do not reach the init function anymore if the DT node is disabled (as this is now handled by OF_DECLARE), so remove the explicit check for that case. This fixes a long standing bogus error when booting ARM's fastmodels. Signed-off-by: Andre Przywara Reviewed-by: Robin Murphy Link: https://lore.kernel.org/r/20220506162522.3675399-1-andre.przywara@arm.com Signed-off-by: Daniel Lezcano Signed-off-by: Sasha Levin

clocksource/drivers/sp804: Enable Hisilicon sp804 timer 64bit mode

2020-09-24T08:51:04Z

A 100MHZ 32-bit timer will be wrapped up less than 43s. Although the kernel maintains a software high 32-bit count in the tick IRQ. But it's not applicable to the user mode APPs. Note: The kernel still uses the lower 32 bits of the timer. Signed-off-by: Zhen Lei Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200918132237.3552-9-thunder.leizhen@huawei.com

clocksource/drivers/sp804: Add support for Hisilicon sp804 timer

2020-09-24T08:51:04Z

clocksource/drivers/sp804: Support non-standard register offset

2020-09-24T08:51:04Z

The ARM SP804 supports a maximum of 32-bit counter, but Hisilicon extends it to 64-bit. That means, the registers: TimerXload, TimerXValue and TimerXBGLoad are 64bits, all other registers are the same as those in the SP804. The driver code can be completely reused except that the register offset is different. Currently, we get a timer register address by: add the constant register offset to the timer base address. e.g. "base + TIMER_CTRL". It can not be dynamically adjusted at run time. So create a new structure "sp804_timer" to record the original registers offset, and create a new structure "sp804_clkevt" to record the calculated registers address. So the "base + TIMER_CTRL" is changed to "clkevt->ctrl", this will faster than "base + timer->ctrl". For example: struct sp804_timer arm_sp804_timer = { .ctrl = TIMER_CTRL, }; struct sp804_clkevt clkevt; clkevt.ctrl = base + arm_sp804_timer.ctrl. - writel(0, base + TIMER_CTRL); + writel(0, clkevt->ctrl); Signed-off-by: Zhen Lei Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200918132237.3552-7-thunder.leizhen@huawei.com

clocksource/drivers/sp804: Prepare for support non-standard register offset

2020-09-24T08:51:04Z

Add two local variables: timer1_base and timer2_base in sp804_of_init(), to avoid repeatedly calculate the base address of timer2, and make it easier to recognize timer1. Hope to make the next patch looks more clear. No functional change. Signed-off-by: Zhen Lei Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200918132237.3552-6-thunder.leizhen@huawei.com

clocksource/drivers/sp804: Remove a mismatched comment

2020-09-24T08:51:04Z

writel(0, base + TIMER_CTRL); ... ... writel(xxx | TIMER_CTRL_PERIODIC, base + TIMER_CTRL); The timer is just temporarily disabled, and it will be set to periodic mode later. The description of the field TimerMode of the register TimerXControl as shown below: 0 = Timer module is in free-running mode (default) 1 = Timer module is in periodic mode. Signed-off-by: Zhen Lei Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200918132237.3552-5-thunder.leizhen@huawei.com

clocksource/drivers/sp804: Delete the leading "__" of some functions

2020-09-24T08:51:04Z

Delete the leading "__" of __sp804_clocksource_and_sched_clock_init() and __sp804_clockevents_init(), make it looks a little more comfortable. Signed-off-by: Zhen Lei Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200918132237.3552-4-thunder.leizhen@huawei.com

clocksource/drivers/sp804: Remove unused sp804_timer_disable() and timer-sp804.h

2020-09-24T08:51:04Z

Since commit 7484c727b636 ("ARM: realview: delete the RealView board files") and commit 16956fed35fe ("ARM: versatile: switch to DT only booting and remove legacy code"), there's no one to use the functions defined or declared in include/clocksource/timer-sp804.h. Delete it. Signed-off-by: Zhen Lei Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200918132237.3552-3-thunder.leizhen@huawei.com

clocksource/drivers/sp804: Cleanup clk_get_sys()

2020-09-24T08:51:04Z

Move the clk_get_sys() part into sp804_get_clock_rate(), cleanup the same code. Signed-off-by: Kefeng Wang Signed-off-by: Zhen Lei Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200918132237.3552-2-thunder.leizhen@huawei.com

clocksource: Replace setup_irq() by request_irq()

2020-02-27T11:15:24Z

request_irq() is preferred over setup_irq(). The early boot setup_irq() invocations happen either via 'init_IRQ()' or 'time_init()', while memory allocators are ready by 'mm_init()'. Per tglx[1], setup_irq() existed in olden days when allocators were not ready by the time early interrupts were initialized. Hence replace setup_irq() by request_irq(). Seldom remove_irq() usage has been observed coupled with setup_irq(), wherever that has been found, it too has been replaced by free_irq(). A build error that was reported by kbuild test robot in the previous version of the patch also has been fixed. [1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos Signed-off-by: afzal mohammed Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/91961c77c1cf93d41523f5e1ac52043f32f97077.1582799709.git.afzal.mohd.ma@gmail.com