<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/crypto, branch v4.9.15</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.9.15</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.9.15'/>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/'/>
<updated>2017-02-14T23:25:33Z</updated>
<entry>
<title>crypto: ccp - Fix double add when creating new DMA command</title>
<updated>2017-02-14T23:25:33Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2017-01-27T23:09:04Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=f77e7b119ff18d4732b6e08b3d10c4e324de9442'/>
<id>urn:sha1:f77e7b119ff18d4732b6e08b3d10c4e324de9442</id>
<content type='text'>
commit e5da5c5667381d2772374ee6a2967b3576c9483d upstream.

Eliminate a double-add by creating a new list to manage
command descriptors when created; move the descriptor to
the pending list when the command is submitted.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>crypto: ccp - Fix DMA operations when IOMMU is enabled</title>
<updated>2017-02-14T23:25:33Z</updated>
<author>
<name>Gary R Hook</name>
<email>gary.hook@amd.com</email>
</author>
<published>2017-01-27T21:28:45Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=1105ccf25118894ffde5b50d43c52b9e39fe3fc9'/>
<id>urn:sha1:1105ccf25118894ffde5b50d43c52b9e39fe3fc9</id>
<content type='text'>
commit 500c0106e638e08c2c661c305ed57d6b67e10908 upstream.

An I/O page fault occurs when the IOMMU is enabled on a
system that supports the v5 CCP.  DMA operations use a
Request ID value that does not match what is expected by
the IOMMU, resulting in the I/O page fault.  Setting the
Request ID value to 0 corrects this issue.

Signed-off-by: Gary R Hook &lt;gary.hook@amd.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>crypto: qat - zero esram only for DH85x devices</title>
<updated>2017-02-14T23:25:33Z</updated>
<author>
<name>Giovanni Cabiddu</name>
<email>giovanni.cabiddu@intel.com</email>
</author>
<published>2016-12-22T15:00:24Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=d7aa88a14eb059cdc9c82206cd3ee8ccb6f62ee6'/>
<id>urn:sha1:d7aa88a14eb059cdc9c82206cd3ee8ccb6f62ee6</id>
<content type='text'>
commit 685ce0626840e2673fe64ea8807684f7324fec5f upstream.

Zero embedded ram in DH85x devices. This is not
needed for newer generations as it is done by HW.

Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>crypto: qat - fix bar discovery for c62x</title>
<updated>2017-02-14T23:25:33Z</updated>
<author>
<name>Giovanni Cabiddu</name>
<email>giovanni.cabiddu@intel.com</email>
</author>
<published>2016-12-22T15:00:12Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=2d5dd056884e147a369aa1f6aa786e65a36e624a'/>
<id>urn:sha1:2d5dd056884e147a369aa1f6aa786e65a36e624a</id>
<content type='text'>
commit 3484ecbe0e9deb94afb0b9b6172d77e98eb72b94 upstream.

Some accelerators of the c62x series have only two bars.
This patch skips BAR0 if the accelerator does not have it.

Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>crypto: chcr - Check device is allocated before use</title>
<updated>2017-02-14T23:25:32Z</updated>
<author>
<name>Harsh Jain</name>
<email>harsh@chelsio.com</email>
</author>
<published>2017-01-24T05:04:33Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=b4de8af91b8ab9a604a5acd78b0d8763cf5818b5'/>
<id>urn:sha1:b4de8af91b8ab9a604a5acd78b0d8763cf5818b5</id>
<content type='text'>
commit f5f7bebc91ab378dea5aad5277c4d283e46472d9 upstream.

Ensure dev is allocated for crypto uld context before using the device
for crypto operations.

Signed-off-by: Atul Gupta &lt;atul.gupta@chelsio.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>crypto: caam - fix AEAD givenc descriptors</title>
<updated>2017-01-06T09:40:13Z</updated>
<author>
<name>Alex Porosanu</name>
<email>alexandru.porosanu@nxp.com</email>
</author>
<published>2016-11-09T08:46:11Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=21cc91554c3da12708c9a85a98ce144409dc21ef'/>
<id>urn:sha1:21cc91554c3da12708c9a85a98ce144409dc21ef</id>
<content type='text'>
commit d128af17876d79b87edf048303f98b35f6a53dbc upstream.

The AEAD givenc descriptor relies on moving the IV through the
output FIFO and then back to the CTX2 for authentication. The
SEQ FIFO STORE could be scheduled before the data can be
read from OFIFO, especially since the SEQ FIFO LOAD needs
to wait for the SEQ FIFO LOAD SKIP to finish first. The
SKIP takes more time when the input is SG than when it's
a contiguous buffer. If the SEQ FIFO LOAD is not scheduled
before the STORE, the DECO will hang waiting for data
to be available in the OFIFO so it can be transferred to C2.
In order to overcome this, first force transfer of IV to C2
by starting the "cryptlen" transfer first and then starting to
store data from OFIFO to the output buffer.

Fixes: 1acebad3d8db8 ("crypto: caam - faster aead implementation")
Signed-off-by: Alex Porosanu &lt;alexandru.porosanu@nxp.com&gt;
Signed-off-by: Horia Geantă &lt;horia.geanta@nxp.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>crypto: caam - fix pointer size for AArch64 boot loader, AArch32 kernel</title>
<updated>2016-12-07T11:55:17Z</updated>
<author>
<name>Horia Geantă</name>
<email>horia.geanta@nxp.com</email>
</author>
<published>2016-12-05T09:06:58Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=39eaf759466f4e3fbeaa39075512f4f345dffdc8'/>
<id>urn:sha1:39eaf759466f4e3fbeaa39075512f4f345dffdc8</id>
<content type='text'>
Start with a clean slate before dealing with bit 16 (pointer size)
of Master Configuration Register.
This fixes the case of AArch64 boot loader + AArch32 kernel, when
the boot loader might set MCFGR[PS] and kernel would fail to clear it.

Cc: &lt;stable@vger.kernel.org&gt;
Reported-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Signed-off-by: Horia Geantă &lt;horia.geanta@nxp.com&gt;
Reviewed-By: Alison Wang &lt;Alison.wang@nxp.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: marvell - Don't corrupt state of an STD req for re-stepped ahash</title>
<updated>2016-12-07T11:55:17Z</updated>
<author>
<name>Romain Perier</name>
<email>romain.perier@free-electrons.com</email>
</author>
<published>2016-12-05T08:56:39Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=9e5f7a149e00d211177f6de8be427ebc72a1c363'/>
<id>urn:sha1:9e5f7a149e00d211177f6de8be427ebc72a1c363</id>
<content type='text'>
mv_cesa_hash_std_step() copies the creq-&gt;state into the SRAM at each
step, but this is only required on the first one. By doing that, we
overwrite the engine state, and get erroneous results when the crypto
request is split in several chunks to fit in the internal SRAM.

This commit changes the function to copy the state only on the first
step.

Fixes: commit 2786cee8e50b ("crypto: marvell - Move SRAM I/O op...")
Signed-off-by: Romain Perier &lt;romain.perier@free-electrons.com&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: marvell - Don't copy hash operation twice into the SRAM</title>
<updated>2016-12-07T11:55:16Z</updated>
<author>
<name>Romain Perier</name>
<email>romain.perier@free-electrons.com</email>
</author>
<published>2016-12-05T08:56:38Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=68c7f8c1c4e9b06e6b153fa3e9e0cda2ef5aaed8'/>
<id>urn:sha1:68c7f8c1c4e9b06e6b153fa3e9e0cda2ef5aaed8</id>
<content type='text'>
No need to copy the template of an hash operation twice into the SRAM
from the step function.

Fixes: commit 85030c5168f1 ("crypto: marvell - Add support for chai...")
Signed-off-by: Romain Perier &lt;romain.perier@free-electrons.com&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: chcr - Fix memory corruption</title>
<updated>2016-11-30T11:46:44Z</updated>
<author>
<name>Harsh Jain</name>
<email>harsh@chelsio.com</email>
</author>
<published>2016-11-29T13:30:34Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=66bf093772040ae8b864d2cf953f2c73005f7815'/>
<id>urn:sha1:66bf093772040ae8b864d2cf953f2c73005f7815</id>
<content type='text'>
Fix memory corruption done by  *((u32 *)dec_key + k)
 operation.

Signed-off-by: Jitendra Lulla &lt;JLULLA@chelsio.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
