user/sven/linux.git/drivers/dma, branch v3.18.84

dmaengine: ep93xx: Always start from BASE0

2017-06-14T10:54:18Z

commit 0037ae47812b1f431cc602100d1d51f37d77b61e upstream. The current buffer is being reset to zero on device_free_chan_resources() but not on device_terminate_all(). It could happen that HW is restarted and expects BASE0 to be used, but the driver is not synchronized and will start from BASE1. One solution is to reset the buffer explicitly in m2p_hw_setup(). Signed-off-by: Alexander Sverdlin Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman

dmaengine: imx-sdma: switch to dynamic context mode after script loaded

2016-05-30T21:56:04Z

[ Upstream commit 855832e47c1e51db701786ed76f8a9fec323aad6 ] Below comments got from Page4724 of Reference Manual of i.mx6q: http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf --"Static context mode should be used for the first channel called after reset to ensure that the all context RAM for that channel is initialized during the context SAVE phase when the channel is done or yields. Subsequent calls to the same channel or different channels may use any of the dynamic context modes. This will ensure that all context locations for the bootload channel are initialized, and prevent undefined values in context RAM from being loaded during the context restore if the channel is re-started later" Unfortunately, the rule was broken by commit(5b28aa319bba96987316425a1131813d87cbab35) .This patch just take them back. Signed-off-by: Robin Gong Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: dw: fix master selection

2016-04-20T13:41:02Z

[ Upstream commit 3fe6409c23e2bee4b2b1b6d671d2da8daa15271c ] The commit 895005202987 ("dmaengine: dw: apply both HS interfaces and remove slave_id usage") cleaned up the code to avoid usage of depricated slave_id member of generic slave configuration. Meanwhile it broke the master selection by removing important call to dwc_set_masters() in ->device_alloc_chan_resources() which copied masters from custom slave configuration to the internal channel structure. Everything works until now since there is no customized connection of DesignWare DMA IP to the bus, i.e. one bus and one or more masters are in use. The configurations where 2 masters are connected to the different masters are not working anymore. We are expecting one user of such configuration and need to select masters properly. Besides that it is obviously a performance regression since only one master is in use in multi-master configuration. Select masters in accordance with what user asked for. Keep this patch in a form more suitable for back porting. We are safe to take necessary data in ->device_alloc_chan_resources() because we don't support generic slave configuration embedded into custom one, and thus the only way to provide such is to use the parameter to a filter function which is called exactly before channel resource allocation. While here, replase BUG_ON to less noisy dev_warn() and prevent channel allocation in case of error. Fixes: 895005202987 ("dmaengine: dw: apply both HS interfaces and remove slave_id usage") Cc: stable@vger.kernel.org Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: dw: disable BLOCK IRQs for non-cyclic xfer

2016-03-04T15:18:42Z

[ Upstream commit ee1cdcdae59563535485a5f56ee72c894ab7d7ad ] The commit 2895b2cad6e7 ("dmaengine: dw: fix cyclic transfer callbacks") re-enabled BLOCK interrupts with regard to make cyclic transfers work. However, this change becomes a regression for non-cyclic transfers as interrupt counters under stress test had been grown enormously (approximately per 4-5 bytes in the UART loop back test). Taking into consideration above enable BLOCK interrupts if and only if channel is programmed to perform cyclic transfer. Fixes: 2895b2cad6e7 ("dmaengine: dw: fix cyclic transfer callbacks") Signed-off-by: Andy Shevchenko Acked-by: Mans Rullgard Tested-by: Mans Rullgard Acked-by: Viresh Kumar Cc: Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: dw: fix cyclic transfer callbacks

2016-02-10T03:56:51Z

[ Upstream commit 2895b2cad6e7a95104cf396e5330054453382ae1 ] Cyclic transfer callbacks rely on block completion interrupts which were disabled in commit ff7b05f29fd4 ("dmaengine/dw_dmac: Don't handle block interrupts"). This re-enables block interrupts so the cyclic callbacks can work. Other transfer types are not affected as they set the INT_EN bit only on the last block. Fixes: ff7b05f29fd4 ("dmaengine/dw_dmac: Don't handle block interrupts") Signed-off-by: Mans Rullgard Reviewed-by: Viresh Kumar Signed-off-by: Vinod Koul Cc: Signed-off-by: Sasha Levin

dmaengine: dw: fix cyclic transfer setup

2016-02-10T03:56:48Z

[ Upstream commit df3bb8a0e619d501cd13334c3e0586edcdcbc716 ] Commit 61e183f83069 ("dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume") moved some channel initialisation to a new function which must be called before starting a transfer. This updates dw_dma_cyclic_start() to use dwc_dostart() like the other modes, thus ensuring dwc_initialize() gets called and removing some code duplication. Fixes: 61e183f83069 ("dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume") Signed-off-by: Mans Rullgard Reviewed-by: Viresh Kumar Signed-off-by: Vinod Koul Cc: Signed-off-by: Sasha Levin

dmaengine: dw: Make error prints unique. Part #1

2016-02-10T03:56:38Z

[ Upstream commit 550da64bc89b597395ea6e43a6b4026491035a9d ] The same error message is printed from different functions. Add a function name to error message in order to make it easier to grep error from sources. Signed-off-by: Jarkko Nikula Acked-by: Viresh Kumar Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: dw: properly read DWC_PARAMS register

2015-10-28T02:13:05Z

[ Upstream commit 6bea0f6d1c47b07be88dfd93f013ae05fcb3d8bf ] In case we have less than maximum allowed channels (8) and autoconfiguration is enabled the DWC_PARAMS read is wrong because it uses different arithmetic to what is needed for channel priority setup. Re-do the caclulations properly. This now works on AVR32 board well. Fixes: fed2574b3c9f (dw_dmac: introduce software emulation of LLP transfers) Cc: yitian.bu@tangramtek.com Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: mv_xor: bug fix for racing condition in descriptors cleanup

2015-07-04T03:02:28Z

[ Upstream commit 9136291f1dbc1d4d1cacd2840fb35f4f3ce16c46 ] This patch fixes a bug in the XOR driver where the cleanup function can be called and free descriptors that never been processed by the engine (which result in data errors). The cleanup function will free descriptors based on the ownership bit in the descriptors. Fixes: ff7b04796d98 ("dmaengine: DMA engine driver for Marvell XOR engine") Signed-off-by: Lior Amsalem Signed-off-by: Maxime Ripard Reviewed-by: Ofer Heifetz Cc: stable@vger.kernel.org Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: shdmac: avoid unused variable warnings

2015-06-28T17:39:26Z

[ Upstream commit 7d3beab16dd9eee86bb1a4dd05b51159fc7772f0 ] This driver uses '#ifdef CONFIG_ARCH_SHMOBILE' and '#ifdef CONFIG_ARM' interchangeably in its sh_dmae_probe function, which causes a build warning when building for ARM without also enabling shmobile: dma/sh/shdmac.c: In function sh_dmae_probe: dma/sh/shdmac.c:696:6: warning: unused variable errirq [-Wunused-variable] dma/sh/shdmac.c:695:16: warning: unused variable irqflags [-Wunused-variable] dma/sh/shdmac.c: At top level: dma/sh/shdmac.c:447:20: warning: sh_dmae_err defined but not used [-Wunused-function] This changes all the #ifdef to test for CONFIG_ARCH_SHMOBILE to avoid that warning. An earlier patch from Laurent had fixed the warning for non-ARM case, but it still remained present in ARM randconfig builds. Signed-off-by: Arnd Bergmann Fixes: 52d6a5ee101bf ("DMA: shdma: Fix warnings due to declared but unused symbols") Acked-by: Laurent Pinchart Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin