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<title>user/sven/linux.git/drivers/dma, branch v4.1.6</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.1.6</id>
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<updated>2015-08-17T03:52:16Z</updated>
<entry>
<title>dmaengine: at_xdmac: fix transfer data width in at_xdmac_prep_slave_sg()</title>
<updated>2015-08-17T03:52:16Z</updated>
<author>
<name>Cyrille Pitchen</name>
<email>cyrille.pitchen@atmel.com</email>
</author>
<published>2015-06-30T12:36:57Z</published>
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<id>urn:sha1:c0e0ec977861b29059691d51a68bf563d3bc218a</id>
<content type='text'>
commit 1c8a38b1268aebc1a903b21b11575077e02d2cf7 upstream.

This patch adds the missing update of the transfer data width in
at_xdmac_prep_slave_sg().

Indeed, for each item in the scatter-gather list, we check whether the
transfer length is aligned with the data width provided by
dmaengine_slave_config(). If so, we directly use this data width for the
current part of the transfer we are preparing. Otherwise, the data width
is reduced to 8 bits (1 byte). Of course, the actual number of register
accesses must also be updated to match the new data width.

So one chunk was missing in the original patch (see Fixes tag below): the
number of register accesses was correctly set to (len &gt;&gt; fixed_dwidth) in
mbr_ubc but the real data width was not updated in mbr_cfg. Since mbr_cfg
may change for each part of the scatter-gather transfer this also explains
why the original patch used the Descriptor View 2 instead of the
Descriptor View 1.

Let's take the example of a DMA transfer to write 8bit data into an Atmel
USART with FIFOs. When FIFOs are enabled in the USART, its Transmit
Holding Register (THR) works in multidata mode, that is to say that up to
4 8bit data can be written into the THR in a single 32bit access and it is
still possible to write only one data with a 8bit access. To take
advantage of this new feature, the DMA driver was modified to allow
multiple dwidths when doing slave transfers.
For instance, when the total length is 22 bytes, the USART driver splits
the transfer into 2 parts:

First part: 20 bytes transferred through 5 32bit writes into THR
Second part: 2 bytes transferred though 2 8bit writes into THR

For the second part, the data width was first set to 4_BYTES by the USART
driver thanks to dmaengine_slave_config() then at_xdmac_prep_slave_sg()
reduces this data width to 1_BYTE because the 2 byte length is not aligned
with the original 4_BYTES data width. Since the data width is modified,
the actual number of writes into THR must be set accordingly.

Signed-off-by: Cyrille Pitchen &lt;cyrille.pitchen@atmel.com&gt;
Fixes: 6d3a7d9e3ada ("dmaengine: at_xdmac: allow muliple dwidths when doing slave transfers")
Cc: stable@vger.kernel.org #4.0 and later
Acked-by: Nicolas Ferre &lt;nicolas.ferre@atmel.com&gt;
Acked-by: Ludovic Desroches &lt;ludovic.desroches@atmel.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>dmaengine: pl330: Really fix choppy sound because of wrong residue calculation</title>
<updated>2015-08-17T03:52:11Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>k.kozlowski.k@gmail.com</email>
</author>
<published>2015-06-15T14:00:09Z</published>
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<id>urn:sha1:e925654834c583e62d08777c6993e20a362a69ac</id>
<content type='text'>
commit 5dd90e5b91e0f5c925b12b132c7cd27538870256 upstream.

When pl330 driver was used during sound playback, after some time or
after a number of plays the sound became choppy or totally noisy. For
example on Odroid XU3 board the first four executions of aplay with
small WAVE worked fine, but fifth was unrecognizable with errors:
	$ aplay /usr/share/sounds/alsa/Front_Right.wava
	underrun!!! (at least 0.095 ms long)

Issue was caused by wrong residue reported by pl330 driver to
pcm_dmaengine for its cyclic dma transfers.

The pl330_tx_status(), residue reporting function, used a "last" flag in
a descriptor to indicate that there is no more data to send.

The pl330_tx_submit() iterated over descriptors trying to remove this
flag from them and then mark last descriptor as "last".  However when
iterating it actually removed the flag not from descriptors but always
from last of it (and then reset it). Thus effectively once some
descriptor was marked as last, then it stayed like this forever causing
residue to be reported too low.

Signed-off-by: Krzysztof Kozlowski &lt;k.kozlowski.k@gmail.com&gt;
Fixes: aee4d1fac887 ("dmaengine: pl330: improve pl330_tx_status() function")
Reported-by: gabriel@unseen.is
Suggested-by: Marek Szyprowski &lt;m.szyprowski@samsung.com&gt;
Tested-by: Lars-Peter Clausen &lt;lars@metafoo.de&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>dmaengine: pl330: Fix overflow when reporting residue in memcpy</title>
<updated>2015-08-17T03:52:11Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>k.kozlowski@samsung.com</email>
</author>
<published>2015-06-15T08:25:16Z</published>
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<id>urn:sha1:9cd4b78cd56489755fcba685b5e1a243cea6e6cf</id>
<content type='text'>
commit ae128293d97404f491dc76f1843c7adacfec3441 upstream.

During memcpy operations the residue was always set to an u32 overflowed
value.

In pl330_tx_status() function number of currently transferred bytes was
subtracted from internal "bytes_requested" field. However this
"bytes_requested" was not initialized at start to length of memcpy
buffer so transferred bytes were subtracted from 0 causing overflow.

Signed-off-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Fixes: aee4d1fac887 ("dmaengine: pl330: improve pl330_tx_status() function")
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>dmaengine: mv_xor: bug fix for racing condition in descriptors cleanup</title>
<updated>2015-08-03T16:29:12Z</updated>
<author>
<name>Lior Amsalem</name>
<email>alior@marvell.com</email>
</author>
<published>2015-05-26T13:07:32Z</published>
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<id>urn:sha1:499b1532e1ee4e3c6ebc1ced5a1d1e75f696262e</id>
<content type='text'>
commit 9136291f1dbc1d4d1cacd2840fb35f4f3ce16c46 upstream.

This patch fixes a bug in the XOR driver where the cleanup function can be
called and free descriptors that never been processed by the engine (which
result in data errors).

The cleanup function will free descriptors based on the ownership bit in
the descriptors.

Fixes: ff7b04796d98 ("dmaengine: DMA engine driver for Marvell XOR engine")
Signed-off-by: Lior Amsalem &lt;alior@marvell.com&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Reviewed-by: Ofer Heifetz &lt;oferh@marvell.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>dmaengine: Fix choppy sound because of unimplemented resume</title>
<updated>2015-06-12T09:52:26Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>k.kozlowski@samsung.com</email>
</author>
<published>2015-06-10T08:17:07Z</published>
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<id>urn:sha1:88d04643c66052a1cf92a6fd5f92dff0f7757f61</id>
<content type='text'>
Some drivers implement only pause operation (no resuming). Example is
pl330 where pause is needed for getting residuum. pl330 does not support
resume operation, transfer must be stopped after pause.

However for slaves this is exposed always as "pause and resume" which
introduces subtle errors on Odroid U3 board (Exynos4412 with pl330).
After adding pause function to pl330 driver the audio playback
(utilizing DMA) gets choppy after some time (approximately 24 hours).

Fix this by exposing "cmd_pause" if and only if pause and resume are
implemented.

Signed-off-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Reported-by: gabriel@unseen.is
Reported-by: Marek Szyprowski &lt;m.szyprowski@samsung.com&gt;
Cc: &lt;stable@vger.kernel.org&gt;
Fixes: 88987d2c7534 ("dmaengine: pl330: add DMA_PAUSE feature")
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: at_xdmac: rework slave configuration part</title>
<updated>2015-06-08T10:57:09Z</updated>
<author>
<name>Ludovic Desroches</name>
<email>ludovic.desroches@atmel.com</email>
</author>
<published>2015-06-08T08:33:15Z</published>
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<id>urn:sha1:765c37d876698268eea8b820081ac8fc9d0fc8bc</id>
<content type='text'>
Rework slave configuration part in order to more report wrong errors
about the configuration.
Only maxburst and addr width values are checked when doing the slave
configuration. The validity of the channel configuration is done at
prepare time.

Signed-off-by: Ludovic Desroches &lt;ludovic.desroches@atmel.com&gt;
Cc: stable@vger.kernel.org # 4.0 and later
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: at_xdmac: lock fixes</title>
<updated>2015-06-08T10:57:09Z</updated>
<author>
<name>Ludovic Desroches</name>
<email>ludovic.desroches@atmel.com</email>
</author>
<published>2015-06-08T08:33:14Z</published>
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<id>urn:sha1:4c374fc7ce944024936a6d9804daec85207d9384</id>
<content type='text'>
Using _bh variant for spin locks causes this kind of warning:
Starting logging: ------------[ cut here ]------------
WARNING: CPU: 0 PID: 3 at /ssd_drive/linux/kernel/softirq.c:151
__local_bh_enable_ip+0xe8/0xf4()
Modules linked in:
CPU: 0 PID: 3 Comm: ksoftirqd/0 Not tainted 4.1.0-rc2+ #94
Hardware name: Atmel SAMA5
[&lt;c0013c04&gt;] (unwind_backtrace) from [&lt;c00118a4&gt;] (show_stack+0x10/0x14)
[&lt;c00118a4&gt;] (show_stack) from [&lt;c001bbcc&gt;]
(warn_slowpath_common+0x80/0xac)
[&lt;c001bbcc&gt;] (warn_slowpath_common) from [&lt;c001bc14&gt;]
(warn_slowpath_null+0x1c/0x24)
[&lt;c001bc14&gt;] (warn_slowpath_null) from [&lt;c001e28c&gt;]
(__local_bh_enable_ip+0xe8/0xf4)
[&lt;c001e28c&gt;] (__local_bh_enable_ip) from [&lt;c01fdbd0&gt;]
(at_xdmac_device_terminate_all+0xf4/0x100)
[&lt;c01fdbd0&gt;] (at_xdmac_device_terminate_all) from [&lt;c02221a4&gt;]
(atmel_complete_tx_dma+0x34/0xf4)
[&lt;c02221a4&gt;] (atmel_complete_tx_dma) from [&lt;c01fe4ac&gt;]
(at_xdmac_tasklet+0x14c/0x1ac)
[&lt;c01fe4ac&gt;] (at_xdmac_tasklet) from [&lt;c001de58&gt;]
(tasklet_action+0x68/0xb4)
[&lt;c001de58&gt;] (tasklet_action) from [&lt;c001dfdc&gt;]
(__do_softirq+0xfc/0x238)
[&lt;c001dfdc&gt;] (__do_softirq) from [&lt;c001e140&gt;] (run_ksoftirqd+0x28/0x34)
[&lt;c001e140&gt;] (run_ksoftirqd) from [&lt;c0033a3c&gt;]
(smpboot_thread_fn+0x138/0x18c)
[&lt;c0033a3c&gt;] (smpboot_thread_fn) from [&lt;c0030e7c&gt;] (kthread+0xdc/0xf0)
[&lt;c0030e7c&gt;] (kthread) from [&lt;c000f480&gt;] (ret_from_fork+0x14/0x34)
---[ end trace b57b14a99c1d8812 ]---

It comes from the fact that devices can called some code from the DMA
controller with irq disabled. _bh variant is not intended to be used in
this case since it can enable irqs. Switch to irqsave/irqrestore variant to
avoid this situation.

Signed-off-by: Ludovic Desroches &lt;ludovic.desroches@atmel.com&gt;
Cc: stable@vger.kernel.org # 4.0 and later
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: hsu: Fix memory leak when stopping a running transfer</title>
<updated>2015-06-02T13:03:08Z</updated>
<author>
<name>Peter Ujfalusi</name>
<email>peter.ujfalusi@ti.com</email>
</author>
<published>2015-05-26T10:11:28Z</published>
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<id>urn:sha1:429770823d961187c39df490d49683c467b10065</id>
<content type='text'>
The vd-&gt;node is removed from the lists when the transfer started so the
vchan_get_all_descriptors() will not find it. This results memory leak.

Signed-off-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
[andy: fix the typo to prevent a compilation error]
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: pl330: Fix hang on dmaengine_terminate_all on certain boards</title>
<updated>2015-05-22T12:31:03Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>k.kozlowski@samsung.com</email>
</author>
<published>2015-05-21T00:34:09Z</published>
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<id>urn:sha1:81cc6edc08705ac0146fe6ac14a0982a31ce6f3d</id>
<content type='text'>
The pl330 device could hang infinitely on certain boards when DMA
channels are terminated.

It was caused by lack of runtime resume when executing
pl330_terminate_all() which calls the _stop() function. _stop() accesses
device register and can loop infinitely while checking for device state.

The hang was confirmed by Dinh Nguyen on Altera SOCFPGA Cyclone V
board during boot. It can be also triggered with:

$ echo 1 &gt; /sys/module/dmatest/parameters/iterations
$ echo dma1chan0 &gt; /sys/module/dmatest/parameters/channel
$ echo 1 &gt; /sys/module/dmatest/parameters/run
$ sleep 1
$ cat /sys/module/dmatest/parameters/run

Reported-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Signed-off-by: Krzysztof Kozlowski &lt;k.kozlowski@samsung.com&gt;
Fixes: ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12")
Cc: &lt;stable@vger.kernel.org&gt;
Tested-by: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: increment privatecnt when using dma_get_any_slave_channel</title>
<updated>2015-04-29T11:17:57Z</updated>
<author>
<name>Christopher Freeman</name>
<email>cfreeman@nvidia.com</email>
</author>
<published>2015-03-04T09:16:58Z</published>
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<id>urn:sha1:63f89caad0e32dcfa17b2d17919816253de48996</id>
<content type='text'>
Channels allocated via dma_get_any_slave_channel were not increasing
the counter tracking private allocations.  When these channels were
released, privatecnt may erroneously fall to zero.  The DMA device
would then lose its DMA_PRIVATE cap and fail to allocate future private
channels (via private_candidate) as any allocations still outstanding
would incorrectly be seen as public allocations.

Signed-off-by: Christopher Freeman &lt;cfreeman@nvidia.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
</feed>
