user/sven/linux.git/drivers/edac/Makefile, branch ipvs/droutbytes

edac: i5100 new intel chipset driver

2008-07-25T17:53:48Z

Preliminary support for the Intel 5100 MCH. CE and UE errors are reported along with the current DIMM label information and other memory parameters. Reasons why this is preliminary: 1) This chip has 2 independent memory controllers which, for best perforance, use interleaved accesses to the DDR2 memory. This architecture does not map very well to the current edac data structures which depend on symmetric channel access to the interleaved data. Without core changes, the best I could do for now is to map both memory controllers to different csrows (first all ranks of controller 0, then all ranks of controller 1). Someone much more familiar with the edac core than I will probably need to come up with a more general data structure to handle the interleaving and de-interleaving of the two memory controllers. 2) I have not yet tackled the de-interleaving of the rank/controller address space into the physical address space of the CPU. There is nothing fundamentally missing, it is just ending up to be a lot of code, and I'd rather keep it separate for now, esp since it doesn't work yet... 3) The code depends on a particular i5100 chip select to DIMM mainboard chip select mapping. This mapping seems obvious to me in order to support dual and single ranked memory, but it is not unique and DIMM labels could be wrong on other mainboards. There is no way to query this mapping that I know of. 4) The code requires that the i5100 is in 32GB mode. Only 4 ranks per controller, 2 ranks per DIMM are supported. I do not have hardware (nor do I expect to have hardware anytime soon) for the 48GB (6 ranks per controller) mode. 5) The serial presence detect code should be broken out into a "real" i2c driver so that decode-dimms.pl can work. Signed-off-by: Arthur Jones Signed-off-by: Doug Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers-edac: add marvell mv64x60 driver

2008-02-07T16:42:23Z

Marvell mv64x60 SoC support for EDAC. Used on PPC and MIPS platforms. Development and testing done on PPC Motorola prpmc2800 ATCA board. [akpm@linux-foundation.org: make mv64x60_ctl_name static] Signed-off-by: Dave Jiang Cc: Alan Cox Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers-edac: add freescale mpc85xx driver

2008-02-07T16:42:23Z

EDAC chip driver support for Freescale MPC85xx platforms. PPC based. Signed-off-by: Dave Jiang Cc: Alan Cox Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers-edac: add Cell MC driver

2008-02-07T16:42:23Z

Adds driver for the Cell memory controller when used without a Hypervisor such as on the IBM Cell blades. There might still be some improvements to do to this such as finding if it's possible to properly obtain more details about the address of the error but it's good enough already to report CE counts which is our main priority at the moment. Signed-off-by: Benjamin Herrenschmidt Cc: Alan Cox Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers/edac: new i82975x driver

2007-07-19T17:04:57Z

New EDAC driver for the i82975x memory controller chipset Used on ASUS motherboards [akpm@linux-foundation.org: fix multiple coding-style bloopers] Signed-off-by: Signed-off-by: Ranganathan Desikan Signed-off-by: Doug Thompson Cc: Greg KH Cc: Alan Cox Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers/edac: new pasemi driver

2007-07-19T17:04:56Z

NEW EDAC driver for the memory controllers on PA Semi PA6T-1682M. Changes since last submission: * Rebased on top of 2.6.22-rc4-mm2 with the EDAC changes merged there. * Minor checkpatch.pl cleanups * Renamed ctl_name * Added dev_name * edac_mc.h -> edac_core.h [akpm@linux-foundation.org: make printk more informative] Cc: Alan Cox alan@lxorguk.ukuu.org.uk Signed-off-by: Egor Martovetsky Signed-off-by: Olof Johansson Signed-off-by: Doug Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers/edac: updated PCI monitoring

2007-07-19T17:04:54Z

Moving PCI to a per-instance device model This should include the correct sysfs setup as well. Please review. Signed-off-by: Dave Jiang Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers/edac: new inte 30x0 MC driver

2007-07-19T17:04:54Z

Here's a driver for the Intel 3000 and 3010 memory controllers, relative to today's Sourceforge code drop. This has only had light testing (I've yet to actually see it handle a memory error) but it detects my hardware correctly. Signed-off-by: Jason Uhlenkott Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers/edac: add new nmi rescan

2007-07-19T17:04:53Z

Provides a way for NMI reported errors on x86 to notify the EDAC subsystem pending ECC errors by writing to a software state variable. Here's the reworked patch. I added an EDAC stub to the kernel so we can have variables that are in the kernel even if EDAC is a module. I also implemented the idea of using the chip driver to select error detection mode via module parameter and eliminate the kernel compile option. Please review/test. Thx! Also, I only made changes to some of the chipset drivers since I am unfamiliar with the other ones. We can add similar changes as we go. Signed-off-by: Dave Jiang Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

drivers/edac: new i82443bxgz MC driver

2007-07-19T17:04:53Z

This is a NEW EDAC Memory Controller driver for the 440BX chipset (I82443BXGX) created and submitted by Timm Small Signed-off-by: Tim Small Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds