user/sven/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v5.4.43

drm/amdgpu/discovery: reserve discovery data at the top of VRAM

2020-01-17T18:48:51Z

commit 5f6a556f98de425fcb7928456839a06f02156633 upstream. IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: Xiaojie Yuan Reviewed-by: Hawking Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amdgpu: introduce vram lost for reset (v2)

2019-08-29T20:52:32Z

for SOC15/vega10 the BACO reset & mode1 would introduce vram lost in high end address range, current kmd's vram lost checking cannot catch it since it only check very ahead visible frame buffer v2: cover NV as well Signed-off-by: Monk Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: simplify and cleanup setting the dma mask

2019-08-15T15:51:01Z

Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by: Christian König Signed-off-by: Christoph Hellwig Signed-off-by: Alex Deucher

drm/amdgpu: add amdgpu_mmhub_funcs definition

2019-08-12T17:47:48Z

add amdgpu_mmhub_funcs definition and initialize it, prepare for mmhub ras enablement Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: remove RREG64/WREG64

2019-08-09T16:17:30Z

atomic 64 bits REG operations are useless currently Reviewed-by: Christian König Reviewed-by: Hawking Zhang Signed-off-by: Tao Zhou Signed-off-by: Alex Deucher

drm/amdgpu: switch to amdgpu_umc structure

2019-07-31T19:49:52Z

create new amdgpu_umc structure to for more umc settings in future and switch to the new structure Signed-off-by: Tao Zhou Signed-off-by: Hawking Zhang Reviewed-by: Dennis Li Signed-off-by: Alex Deucher

drm/amdgpu: add RREG64/WREG64(_PCIE) operations

2019-07-31T19:49:40Z

add 64 bits register access functions v2: implement 64 bit functions in low level Signed-off-by: Tao Zhou Reviewed-by: Dennis Li Signed-off-by: Alex Deucher

drm/amdgpu: add amdgpu_umc_functions structure

2019-07-31T19:48:57Z

This is common structure as UMC callback function Signed-off-by: Hawking Zhang Reviewed-by: Dennis Li Signed-off-by: Alex Deucher

drm/amdgpu: init RSMU and UMC ip base address for vega20

2019-07-31T19:48:51Z

the driver needs to program RSMU and UMC registers to support vega20 RAS feature Signed-off-by: Hawking Zhang Reviewed-by: Dennis Li Signed-off-by: Alex Deucher

drm/amdgpu: put the SMC into the proper state on reset/unload

2019-07-31T04:24:44Z

When doing a GPU reset or unloading the driver, we need to put the SMU into the apprpriate state for the re-init after the reset or unload to reliably work. I don't think this is necessary for BACO because the SMU actually controls the BACO state to it needs to be active. For suspend (S3), the asic is put into D3 so the SMU would be powered down so I don't think we need to put the SMU into any special state. Reviewed-by: Evan Quan Signed-off-by: Alex Deucher