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<title>user/sven/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c, branch v6.9.12</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2024-07-11T10:51:21Z</updated>
<entry>
<title>drm/amdkfd: Let VRAM allocations go to GTT domain on small APUs</title>
<updated>2024-07-11T10:51:21Z</updated>
<author>
<name>Lang Yu</name>
<email>Lang.Yu@amd.com</email>
</author>
<published>2024-04-26T06:56:35Z</published>
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<id>urn:sha1:8d656c7a0fed8e1675a170d0d17039fe713beb59</id>
<content type='text'>
[ Upstream commit eb853413d02c8d9b27942429b261a9eef228f005 ]

Small APUs(i.e., consumer, embedded products) usually have a small
carveout device memory which can't satisfy most compute workloads
memory allocation requirements.

We can't even run a Basic MNIST Example with a default 512MB carveout.
https://github.com/pytorch/examples/tree/main/mnist. Error Log:

"torch.cuda.OutOfMemoryError: HIP out of memory. Tried to allocate
84.00 MiB. GPU 0 has a total capacity of 512.00 MiB of which 0 bytes
is free. Of the allocated memory 103.83 MiB is allocated by PyTorch,
and 22.17 MiB is reserved by PyTorch but unallocated"

Though we can change BIOS settings to enlarge carveout size,
which is inflexible and may bring complaint. On the other hand,
the memory resource can't be effectively used between host and device.

The solution is MI300A approach, i.e., let VRAM allocations go to GTT.
Then device and host can flexibly and effectively share memory resource.

v2: Report local_mem_size_private as 0. (Felix)

Signed-off-by: Lang Yu &lt;Lang.Yu@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;felix.kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Init zone device and drm client after mode-1 reset on reload</title>
<updated>2024-03-20T17:12:57Z</updated>
<author>
<name>Ahmad Rehman</name>
<email>Ahmad.Rehman@amd.com</email>
</author>
<published>2024-03-04T21:56:00Z</published>
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<id>urn:sha1:f679fd6057fbf5ab34aaee28d58b7f81af0cbf48</id>
<content type='text'>
In passthrough environment, when amdgpu is reloaded after unload, mode-1
is triggered after initializing the necessary IPs, That init does not
include KFD, and KFD init waits until the reset is completed. KFD init
is called in the reset handler, but in this case, the zone device and
drm client is not initialized, causing app to create kernel panic.

v2: Removing the init KFD condition from amdgpu_amdkfd_drm_client_create.
As the previous version has the potential of creating DRM client twice.

v3: v2 patch results in SDMA engine hung as DRM open causes VM clear to SDMA
before SDMA init. Adding the condition to in drm client creation, on top of v1,
to guard against drm client creation call multiple times.

Signed-off-by: Ahmad Rehman &lt;Ahmad.Rehman@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Skip packet submission on fatal error</title>
<updated>2024-02-26T16:14:31Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2024-02-22T09:24:50Z</published>
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<id>urn:sha1:e1f6746f339c9514c0564bab02c3f8847f4aa44b</id>
<content type='text'>
If fatal error is detected, packet submission won't go through. Return
error in such cases. Also, avoid waiting for fence when fatal error is
detected.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move the drm client creation behind drm device registration</title>
<updated>2024-01-29T20:35:13Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2024-01-25T04:00:34Z</published>
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<id>urn:sha1:c0125b848abecfbc944bebe2cab076f09455b230</id>
<content type='text'>
This patch is to eliminate interrupt warning below:

  "[drm] Fence fallback timer expired on ring sdma0.0".

An early vm pt clearing job is sent to SDMA ahead of interrupt enabled.
And re-locating the drm client creation following after drm_dev_register
looks like a more proper flow.

v2: wrap the drm client creation

Fixes: 1819200166ce ("drm/amdkfd: Export DMABufs from KFD using GEM handles")
Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;felix.kuehling@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Support passing poison consumption ras block to SRIOV</title>
<updated>2024-01-25T19:58:03Z</updated>
<author>
<name>YiPeng Chai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2024-01-23T08:08:11Z</published>
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<id>urn:sha1:ed1e1e42fd68b073fc47aefe94d70364f3a43e97</id>
<content type='text'>
Support passing poison consumption ras blocks
to SRIOV.

Signed-off-by: YiPeng Chai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable GFXOFF for Compute on GFX11</title>
<updated>2024-01-18T20:46:56Z</updated>
<author>
<name>Ori Messinger</name>
<email>Ori.Messinger@amd.com</email>
</author>
<published>2023-11-22T05:12:13Z</published>
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<id>urn:sha1:776b0953aba8b10cc2903c958d60334c9703dc34</id>
<content type='text'>
On GFX version 11, GFXOFF was disabled due to a MES KIQ firmware
issue, which has since been fixed after version 64.
This patch only re-enables GFXOFF for GFX version 11 if the GPU's
MES KIQ firmware version is newer than version 64.

V2: Keep GFXOFF disabled on GFX11 if MES KIQ is below version 64.
V3: Add parentheses to avoid GCC warning for parentheses:
"suggest parentheses around comparison in operand of ‘&amp;’"
V4: Remove "V3" from commit title
V5: Change commit description and insert 'Acked-by'

Signed-off-by: Ori Messinger &lt;Ori.Messinger@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Harish Kasiviswanathan &lt;Harish.Kasiviswanathan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: init drm_client with funcs hook</title>
<updated>2024-01-18T20:41:08Z</updated>
<author>
<name>Flora Cui</name>
<email>flora.cui@amd.com</email>
</author>
<published>2024-01-10T11:23:56Z</published>
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<id>urn:sha1:733965a90f885de5e9626d383c7605a0a7850074</id>
<content type='text'>
otherwise drm_client_dev_unregister() would try to
kfree(&amp;adev-&gt;kfd.client).

Fixes: 1819200166ce ("drm/amdkfd: Export DMABufs from KFD using GEM handles")
Signed-off-by: Flora Cui &lt;flora.cui@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;felix.kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Export DMABufs from KFD using GEM handles</title>
<updated>2023-12-13T20:09:55Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2023-08-24T18:41:30Z</published>
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<id>urn:sha1:1819200166ce511ac298dc96b9b17eb655a9edc4</id>
<content type='text'>
Create GEM handles for exporting DMABufs using GEM-Prime APIs. The GEM
handles are created in a drm_client_dev context to avoid exposing them
in user mode contexts through a DMABuf import.

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Ramesh Errabolu &lt;Ramesh.Errabolu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update xgmi num links info post gc9.4.2</title>
<updated>2023-11-29T21:48:45Z</updated>
<author>
<name>Jonathan Kim</name>
<email>jonathan.kim@amd.com</email>
</author>
<published>2023-11-16T18:57:07Z</published>
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<id>urn:sha1:35c425f5cc251417ad681475dc9901ab6d3244ea</id>
<content type='text'>
GC IP 9.4.2 and up support TA reporting of the number
of xGMI links between peers.

Tested-by: Vignesh Chander &lt;vignesh.chander@amd.com&gt;
Signed-off-by: Jonathan Kim &lt;jonathan.kim@amd.com&gt;
Reviewed-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Move TLB flushing logic into amdgpu</title>
<updated>2023-11-17T14:29:53Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2023-02-24T23:22:32Z</published>
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<id>urn:sha1:94e2dae0a8bfd456abfd866f1eee8342f0858012</id>
<content type='text'>
This will make it possible for amdgpu GEM ioctls to flush TLBs on compute
VMs.

This removes VMID-based TLB flushing and always uses PASID-based
flushing. This still works because it scans the VMID-PASID mapping
registers to find the right VMID. It's only slightly less efficient. This
is not a production use case.

Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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