<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c, branch v4.4.271</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.4.271</id>
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<updated>2017-07-05T12:37:19Z</updated>
<entry>
<title>drm/amdgpu: check ring being ready before using</title>
<updated>2017-07-05T12:37:19Z</updated>
<author>
<name>Ding Pixel</name>
<email>pding@amd.com</email>
</author>
<published>2017-01-18T09:26:38Z</published>
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<id>urn:sha1:d3be5e0471abd6b517fca283186b1039c6d337d1</id>
<content type='text'>
[ Upstream commit c5f21c9f878b8dcd54d0b9739c025ca73cb4c091 ]

Return success when the ring is properly initialized, otherwise return
failure.

Tonga SRIOV VF doesn't have UVD and VCE engines, the initialization of
these IPs is bypassed. The system crashes if application submit IB to
their rings which are not ready to use. It could be a common issue if
IP having ring buffer is disabled for some reason on specific ASIC, so
it should check the ring being ready to use.

Bug: amdgpu_test crashes system on Tonga VF.

Signed-off-by: Ding Pixel &lt;Pixel.Ding@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;alexander.levin@verizon.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix user fence handling</title>
<updated>2015-12-16T22:48:59Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-12-14T15:42:31Z</published>
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<id>urn:sha1:91acbeb68ab10c0c0f65f30b5b7fddbde4c97dd2</id>
<content type='text'>
This fixes a random corruption under memory pressure. We need to fence
the BO for the user fence as well, otherwise it might be swapped out
and the GPU could write the fence value to an undesired location.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: take a BO reference for the user fence</title>
<updated>2015-12-04T18:05:44Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-12-03T18:55:52Z</published>
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<id>urn:sha1:f3f1769283b8dbf047c678da95b72194ac2477a1</id>
<content type='text'>
No need for a GEM reference here.

Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove vm-&gt;mutex</title>
<updated>2015-11-20T23:22:28Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2015-11-13T07:22:04Z</published>
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<id>urn:sha1:e98c1b0de6fe73f488df62d83d83f377b1b6e2b8</id>
<content type='text'>
Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup scheduler command submission</title>
<updated>2015-11-18T16:39:12Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-11-14T20:05:35Z</published>
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<id>urn:sha1:984810fc45389c545719fbb4219e8a12b27032a4</id>
<content type='text'>
Unify the two code path again, cause they do pretty much the same thing.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;davdi1.zhou@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix handling order in scheduler CS</title>
<updated>2015-11-16T16:05:59Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-11-13T12:04:50Z</published>
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<id>urn:sha1:5d82730af746abca2aa74e00de6370d338df7e95</id>
<content type='text'>
We need to clear parser.ibs and num_ibs before amd_sched_fence_create,
otherwise the IB could be freed twice if fence creates fails.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix incorrect mutex usage v3</title>
<updated>2015-11-16T16:05:58Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-11-05T18:49:48Z</published>
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<id>urn:sha1:e284022163716ecf11c37fd1057c35d689ef2c11</id>
<content type='text'>
Before this patch the scheduler fence was created when we push the job
into the queue, so we could only get the fence after pushing it.

The mutex now was necessary to prevent the thread pushing the jobs to
the hardware from running faster than the thread pushing the jobs into
the queue.

Otherwise the thread pushing jobs into the queue would have accessed
possible freed up memory when it tries to get a reference to the fence.

So what you get in the end is thread A:
mutex_lock(&amp;job-&gt;lock);
...
Kick of thread B.
...
mutex_unlock(&amp;job-&gt;lock);

And thread B:
mutex_lock(&amp;job-&gt;lock);
....
mutex_unlock(&amp;job-&gt;lock);
kfree(job);

I'm actually not sure if I'm still up to date on this, but this usage
pattern used to be not allowed with mutexes. See here as well
https://lwn.net/Articles/575460/.

v2: remove unrelated changes, fix missing owner
v3: rebased, add more commit message

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add command submission workflow tracepoint</title>
<updated>2015-11-16T16:05:57Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2015-11-11T06:56:00Z</published>
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<id>urn:sha1:7034decf6a5b1ff778d83ff9d7ce1f0b404804e4</id>
<content type='text'>
OGL needs these tracepoints to investigate performance issue.

Change-Id: I5e58187d061253f7d665dfce8e4e163ba91d3e2b
Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup amdgpu_cs_parser handling</title>
<updated>2015-11-16T16:05:52Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-11-04T14:44:39Z</published>
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<id>urn:sha1:7e52a81c2f0326a85d3ebc005829bcd604731c6d</id>
<content type='text'>
No need any more to allocate that structure dynamically, just put it on the
stack. This is a start to cleanup some of the scheduler fallouts.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix leaking the IBs on error</title>
<updated>2015-11-16T16:05:51Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2015-11-05T16:00:25Z</published>
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<id>urn:sha1:e4a58a28b50f30e72292b6659d94410cbf7355ad</id>
<content type='text'>
Fixing a memory leak when the scheduler is enabled.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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