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<title>user/sven/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c, branch v4.9.80</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.9.80</id>
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<updated>2016-09-28T02:08:49Z</updated>
<entry>
<title>Merge tag 'v4.8-rc8' into drm-next</title>
<updated>2016-09-28T02:08:49Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2016-09-28T02:08:49Z</published>
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<id>urn:sha1:ca09fb9f60b5f3ab2d57e761aaeea89a5147d784</id>
<content type='text'>
Linux 4.8-rc8

There was a lot of fallout in the imx/amdgpu/i915 drivers, so backmerge
it now to avoid troubles.

* tag 'v4.8-rc8': (1442 commits)
  Linux 4.8-rc8
  fault_in_multipages_readable() throws set-but-unused error
  mm: check VMA flags to avoid invalid PROT_NONE NUMA balancing
  radix tree: fix sibling entry handling in radix_tree_descend()
  radix tree test suite: Test radix_tree_replace_slot() for multiorder entries
  fix memory leaks in tracing_buffers_splice_read()
  tracing: Move mutex to protect against resetting of seq data
  MIPS: Fix delay slot emulation count in debugfs
  MIPS: SMP: Fix possibility of deadlock when bringing CPUs online
  mm: delete unnecessary and unsafe init_tlb_ubc()
  huge tmpfs: fix Committed_AS leak
  shmem: fix tmpfs to handle the huge= option properly
  blk-mq: skip unmapped queues in blk_mq_alloc_request_hctx
  MIPS: Fix pre-r6 emulation FPU initialisation
  arm64: kgdb: handle read-only text / modules
  arm64: Call numa_store_cpu_info() earlier.
  locking/hung_task: Fix typo in CONFIG_DETECT_HUNG_TASK help text
  nvme-rdma: only clear queue flags after successful connect
  i2c: qup: skip qup_i2c_suspend if the device is already runtime suspended
  perf/core: Limit matching exclusive events to one PMU
  ...
</content>
</entry>
<entry>
<title>drm/amdgpu: use the new ring ib and dma frame size callbacks (v2)</title>
<updated>2016-09-16T19:53:03Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-09-16T15:02:34Z</published>
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<id>urn:sha1:9a9db6ef7cf486f4849fe6bb8619009b5fd66399</id>
<content type='text'>
Use them to more accurately determine the ring size required
for ib submission.

v2: drop extra alignment

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:implement CONTEXT_CONTROL (v5)</title>
<updated>2016-09-14T19:10:29Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2016-08-26T05:28:28Z</published>
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<id>urn:sha1:753ad49c9fdfc732972b0d03f2889f473ed35e59</id>
<content type='text'>
v1:
for gfx8, use CONTEXT_CONTROL package to dynamically
skip preamble CEIB and other load_xxx command in sequence.

v2:
support GFX7 as well.
remove cntxcntl in compute ring funcs because CPC doesn't
support this packet.

v3: fix reduntant judgement in cntxcntl.
v4: some cleanups, don't change cs_submit()
v5: keep old MESA supported &amp; bump up KMS version.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Ack-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: change job-&gt;ctx field name</title>
<updated>2016-09-12T22:12:17Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2016-08-25T07:40:48Z</published>
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<id>urn:sha1:3aecd24c65b9539b6faac2a52a9aaa7bc90f4677</id>
<content type='text'>
job-&gt;ctx actually is a fence_context of the entity
it belongs to, naming it as ctx is too vague, and
we'll need add amdgpu_ctx into the job structure
later.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: record error code when ring test failed</title>
<updated>2016-08-31T16:45:56Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2016-08-30T09:59:11Z</published>
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<id>urn:sha1:1f703e6679f373f5bba4efe7093aa82e91af4037</id>
<content type='text'>
Otherwise we may miss errors.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu:add switch buffer to end of CS (v2)</title>
<updated>2016-08-30T21:55:45Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2016-08-26T06:12:37Z</published>
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<id>urn:sha1:c2167a659cc91075417018b88437da86633bb455</id>
<content type='text'>
sync switch buffer scheme with windows kmd for gfx v8,
step1: append a switch_buffer to the end of CS

v2:rebase on latest staging

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Print ring name in amdgpu_ib_schedule()</title>
<updated>2016-08-23T17:48:07Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2016-08-22T14:54:28Z</published>
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<id>urn:sha1:1b5836492de6a753f6bb420f500848761c6f84f3</id>
<content type='text'>
If the ring isn't ready lets print out which ring name
to help debugging.

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: increase timeout of IB test</title>
<updated>2016-07-29T18:37:07Z</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2016-07-26T05:56:31Z</published>
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<id>urn:sha1:bb7ad55b8a2be632714c88e6e611fe2cea3481d7</id>
<content type='text'>
we should give enough time to IB test.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add a fence timeout for the IB tests v2</title>
<updated>2016-07-29T18:37:04Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-07-05T19:07:17Z</published>
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<id>urn:sha1:bbec97aae660adafa5208c5defc54e3cbbe6b129</id>
<content type='text'>
10ms should be enough for now.

v2: fix some typos in CIK code

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Reviewed-by: Edward O'Callaghan &lt;funfunctor@folklore1984.net&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup hw reference handling in the IB tests</title>
<updated>2016-07-14T20:46:05Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-07-05T12:48:17Z</published>
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<id>urn:sha1:22a77cf6d87e0cfadf91bf7d09bae71359bc85f6</id>
<content type='text'>
Reference should be taken when we make the assignment, not anywhere else.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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