<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c, branch v5.4.23</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.4.23</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.4.23'/>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/'/>
<updated>2019-08-02T15:17:21Z</updated>
<entry>
<title>drm/amdgpu: cleanup vega10 SRIOV code path</title>
<updated>2019-08-02T15:17:21Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2019-07-30T09:21:19Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=4cd4c5c064bd5cb9045bab3ed79bce292504d5b8'/>
<id>urn:sha1:4cd4c5c064bd5cb9045bab3ed79bce292504d5b8</id>
<content type='text'>
we can simplify all those unnecessary function under
SRIOV for vega10 since:
1) PSP L1 policy is by force enabled in SRIOV
2) original logic always set all flags which make itself
   a dummy step

besides,
1) the ih_doorbell_range set should also be skipped
for VEGA10 SRIOV.
2) the gfx_common registers should also be skipped
for VEGA10 SRIOV.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Hardcode reg access using L1 security</title>
<updated>2019-06-11T17:39:51Z</updated>
<author>
<name>Trigger Huang</name>
<email>Trigger.Huang@amd.com</email>
</author>
<published>2019-06-03T08:48:17Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=e0301317acfed896c3bcbcbdf33f67f55c9d602b'/>
<id>urn:sha1:e0301317acfed896c3bcbcbdf33f67f55c9d602b</id>
<content type='text'>
Under Vega10 SR-IOV VF, L1 register access mode should be enabled by
default as the non-security VF will no longer be supported.

Signed-off-by: Trigger Huang &lt;Trigger.Huang@amd.com&gt;
Reviewed-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: init vega10 SR-IOV reg access mode</title>
<updated>2019-05-24T17:20:50Z</updated>
<author>
<name>Trigger Huang</name>
<email>Trigger.Huang@amd.com</email>
</author>
<published>2019-05-09T09:32:59Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=78d481126795e9e4740204df95572d9731a6d34e'/>
<id>urn:sha1:78d481126795e9e4740204df95572d9731a6d34e</id>
<content type='text'>
Set different register access mode according to the features
provided by firmware

Signed-off-by: Trigger Huang &lt;Trigger.Huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable separate timeout setting for every ring type V4</title>
<updated>2019-05-24T17:20:48Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-04-29T08:51:17Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=912dfc846aad77e4a61ac39ca92bd7149062e590'/>
<id>urn:sha1:912dfc846aad77e4a61ac39ca92bd7149062e590</id>
<content type='text'>
Every ring type can have its own timeout setting.

 - V2: update lockup_timeout parameter format and cosmetic fixes
 - V3: invalidate 0 and negative values
 - V4: update lockup_timeout parameter format

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add IDH_QUERY_ALIVE event for SR-IOV</title>
<updated>2019-05-06T14:36:48Z</updated>
<author>
<name>Trigger Huang</name>
<email>Trigger.Huang@amd.com</email>
</author>
<published>2019-04-30T08:23:29Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=b6818520edb0dc83d8de807cb40dff44995eab86'/>
<id>urn:sha1:b6818520edb0dc83d8de807cb40dff44995eab86</id>
<content type='text'>
SR-IOV host side will send IDH_QUERY_ALIVE to guest VM to check
if this guest VM is still alive (not destroyed). The only thing
guest KMD need to do is to send ACK back to host.

Signed-off-by: Trigger Huang &lt;Trigger.Huang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support dpm level modification under virtualization v3</title>
<updated>2019-04-10T18:53:27Z</updated>
<author>
<name>Yintian Tao</name>
<email>yttao@amd.com</email>
</author>
<published>2019-04-09T12:33:20Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=bb5a2bdf36a8df79e1437b443299b7fe1ea3abfc'/>
<id>urn:sha1:bb5a2bdf36a8df79e1437b443299b7fe1ea3abfc</id>
<content type='text'>
Under vega10 virtualuzation, smu ip block will not be added.
Therefore, we need add pp clk query and force dpm level function
at amdgpu_virt_ops to support the feature.

v2: add get_pp_clk existence check and use kzalloc to allocate buf

v3: return -ENOMEM for allocation failure and correct the coding style

Signed-off-by: Yintian Tao &lt;yttao@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: tighten gpu_recover in mailbox_flr to avoid duplicate recover in sriov</title>
<updated>2019-02-13T22:50:13Z</updated>
<author>
<name>wentalou</name>
<email>Wentao.Lou@amd.com</email>
</author>
<published>2019-01-30T03:13:01Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=2c11ee6ae5533821cf2c64972d6cb5aa4ab4a46e'/>
<id>urn:sha1:2c11ee6ae5533821cf2c64972d6cb5aa4ab4a46e</id>
<content type='text'>
sriov's gpu_recover inside xgpu_ai_mailbox_flr_work would cause duplicate recover in TDR.
TDR's gpu_recover would be triggered by amdgpu_job_timedout,
that could avoid vk-cts failure by unexpected recover.

Signed-off-by: Wentao Lou &lt;Wentao.Lou@amd.com&gt;
Acked-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/sriov:Correct pfvf exchange logic</title>
<updated>2019-01-14T20:04:24Z</updated>
<author>
<name>Emily Deng</name>
<email>Emily.Deng@amd.com</email>
</author>
<published>2018-12-29T09:46:05Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=d3c117e564bfbfe3c4568aca136be3880ddf4200'/>
<id>urn:sha1:d3c117e564bfbfe3c4568aca136be3880ddf4200</id>
<content type='text'>
The pfvf exchange need be in exclusive mode. And add pfvf exchange in gpu
reset.

Signed-off-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Reviewed-By: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: cleanup GPU recovery check a bit (v2)</title>
<updated>2018-08-27T16:11:16Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-08-21T08:45:29Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=12938fad234a3924cc9b82080db4f62fe1cf52bb'/>
<id>urn:sha1:12938fad234a3924cc9b82080db4f62fe1cf52bb</id>
<content type='text'>
Check if we should call the function instead of providing the forced
flag.

v2: rebase on KFD changes (Alex)

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Acked-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/sriov: Need to set in_gpu_reset flag to back after gpu reset</title>
<updated>2018-05-15T18:44:06Z</updated>
<author>
<name>Emily Deng</name>
<email>Emily.Deng@amd.com</email>
</author>
<published>2018-04-26T10:02:14Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=6e9c2b88eb42bdda6ba1f1a39238c446782d443e'/>
<id>urn:sha1:6e9c2b88eb42bdda6ba1f1a39238c446782d443e</id>
<content type='text'>
After host os reset gpu reset, need to set flag in_gpu_reset to
zero.

Signed-off-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Reviewed-by: Monk Liu &lt;monk.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
