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<title>user/sven/linux.git/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h, branch v4.14.151</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.14.151</id>
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<updated>2017-07-14T15:05:52Z</updated>
<entry>
<title>drm/amdgpu: Support passing amdgpu critical error to host via GPU Mailbox.</title>
<updated>2017-07-14T15:05:52Z</updated>
<author>
<name>Gavin Wan</name>
<email>Gavin.Wan@amd.com</email>
</author>
<published>2017-06-23T17:55:15Z</published>
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<id>urn:sha1:890419409a3aba2ca7185a824e47d8ded8df11a2</id>
<content type='text'>
This feature works for SRIOV enviroment. For non-SRIOV enviroment, the
trans_error function does nothing.

The error information includes error_code (16bit), error_flags(16bit)
and error_data(64bit). Since there are not many errors, we keep the
errors in an array and transfer all errors to Host before amdgpu
initialization function (amdgpu_device_init) exit.

Signed-off-by: Gavin Wan &lt;Gavin.Wan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/virt: increase mailbox timeout to 5000ms</title>
<updated>2017-03-30T03:52:38Z</updated>
<author>
<name>Pixel Ding</name>
<email>Pixel.Ding@amd.com</email>
</author>
<published>2017-01-24T07:04:48Z</published>
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<id>urn:sha1:4726214c542d3b547bd48587cd741d00cdb5086b</id>
<content type='text'>
When multiple VFs try to enter exclusive mode at the same time, the
looping mechansim doesn't help to ensure each can get it because it
only loops active VFs, then the last one has to wait for a long
interval.

Signed-off-by: Pixel Ding &lt;Pixel.Ding@amd.com&gt;
Reviewed-by: Xiangliang.Yu &lt;Xiangliang.Yu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/virt: implement VI virt operation interfaces</title>
<updated>2017-01-27T16:13:24Z</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-01-12T07:00:41Z</published>
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<id>urn:sha1:ab71ac56f6d832443fcd9f884460263b2dc3ff6b</id>
<content type='text'>
VI has asic specific virt support, which including mailbox and
golden registers init.

Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Signed-off-by: shaoyunl &lt;Shaoyun.Liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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