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<title>user/sven/linux.git/drivers/gpu/drm/amd/amdgpu/si.c, branch v4.14.18</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.14.18</id>
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<updated>2017-08-15T06:16:58Z</updated>
<entry>
<title>Backmerge tag 'v4.13-rc5' into drm-next</title>
<updated>2017-08-15T06:16:58Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2017-08-15T06:16:58Z</published>
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<id>urn:sha1:0c697fafc66830ca7d5dc19123a1d0641deaa1f6</id>
<content type='text'>
Linux 4.13-rc5

There's a really nasty nouveau collision, hopefully someone can take a look
once I pushed this out.
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix undue fallthroughs in golden registers initialization</title>
<updated>2017-08-02T18:29:42Z</updated>
<author>
<name>Jean Delvare</name>
<email>jdelvare@suse.de</email>
</author>
<published>2017-07-30T08:18:25Z</published>
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<id>urn:sha1:5694785cf09bf0e7bd8e5f62361ea34fa162a4a0</id>
<content type='text'>
As I was staring at the si_init_golden_registers code, I noticed that
the Pitcairn initialization silently falls through the Cape Verde
initialization, and the Oland initialization falls through the Hainan
initialization. However there is no comment stating that this is
intentional, and the radeon driver doesn't have any such fallthrough,
so I suspect this is not supposed to happen.

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: "Marek Olšák" &lt;maraeo@gmail.com&gt;
Cc: "Christian König" &lt;christian.koenig@amd.com&gt;
Cc: Flora Cui &lt;Flora.Cui@amd.com&gt;
Reviewed-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: implement si_read_bios_from_rom</title>
<updated>2017-07-14T15:06:40Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-07-12T13:18:07Z</published>
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<id>urn:sha1:6d949d247379ec92e1a0642fc7a227284488360e</id>
<content type='text'>
This allows us to read the vbios image directly from ROM.
This is already implemented for other asics, but was not
yet available for SI.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux into drm-next</title>
<updated>2017-06-15T23:56:53Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2017-06-15T23:54:02Z</published>
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<id>urn:sha1:04d4fb5fa63876d8e7cf67f2788aecfafc6a28a7</id>
<content type='text'>
New radeon and amdgpu features for 4.13:
- Lots of Vega10 bug fixes
- Preliminary Raven support
- KIQ support for compute rings
- MEC queue management rework from Andres
- Audio support for DCE6
- SR-IOV improvements
- Improved module parameters for controlling radeon vs amdgpu support
  for SI and CIK
- Bug fixes
- General code cleanups

[airlied: dropped drmP.h header from one file was needed and build broke]

* 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux: (362 commits)
  drm/amdgpu: Fix compiler warnings
  drm/amdgpu: vm_update_ptes remove code duplication
  drm/amd/amdgpu: Port VCN over to new SOC15 macros
  drm/amd/amdgpu: Port PSP v10.0 over to new SOC15 macros
  drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros
  drm/amd/amdgpu: Port NBIO v7.0 driver over to new SOC15 macros
  drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macros
  drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros
  drm/amd/amdgpu: Port MMHUB over to new SOC15 macros
  drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns
  drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros
  drm/amd/amdgpu: Add offset variant to SOC15 macros
  drm/amd/powerplay: add avfs control for Vega10
  drm/amdgpu: add virtual display support for raven
  drm/amdgpu/gfx9: fix compute ring doorbell index
  drm/amd/amdgpu: Rename KIQ ring to avoid spaces
  drm/amd/amdgpu: gfx9 tidy ups (v2)
  drm/amdgpu: add contiguous flag in ucode bo create
  drm/amdgpu: fix missed gpu info firmware when cache firmware during S3
  drm/amdgpu: export test ib debugfs interface
  ...
</content>
</entry>
<entry>
<title>drm/amdgpu: drop support for untouched registers</title>
<updated>2017-05-24T21:40:01Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-04-12T10:49:54Z</published>
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<id>urn:sha1:97fcc76b67b8366633971fd5841a4606d040b67b</id>
<content type='text'>
I couldn't figure out what this was original good for, but we
don't use it any more.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: fix include notation and remove -Iinclude/drm flag</title>
<updated>2017-05-16T15:17:41Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-04-24T04:50:21Z</published>
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<id>urn:sha1:248a1d6f1ac410d3ed3907c1be2502e286f59bb8</id>
<content type='text'>
Include &lt;drm/*.h&gt; instead of relative path from include/drm, then
remove the -Iinclude/drm compiler flag.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Link: http://patchwork.freedesktop.org/patch/msgid/1493009447-31524-4-git-send-email-yamada.masahiro@socionext.com
</content>
</entry>
<entry>
<title>drm/amdgpu: add asic callback to get memsize register</title>
<updated>2017-03-30T03:53:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-03-03T22:26:10Z</published>
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<id>urn:sha1:bbf282d884793f95b89dc35059f8703eaf48ca00</id>
<content type='text'>
Newer asics use different registers so abstract it.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: refine si_read_register</title>
<updated>2017-02-08T22:24:26Z</updated>
<author>
<name>Flora Cui</name>
<email>Flora.Cui@amd.com</email>
</author>
<published>2017-02-07T07:24:25Z</published>
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<id>urn:sha1:dd5dfa61b4ff0165a8436f906ff377e9767ad2cf</id>
<content type='text'>
Signed-off-by: Flora Cui &lt;Flora.Cui@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move misc si headers into amdgpu</title>
<updated>2017-01-27T17:20:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-01-24T23:00:57Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=689957b12b6315c63bd8cce879e2b259a8a4b666'/>
<id>urn:sha1:689957b12b6315c63bd8cce879e2b259a8a4b666</id>
<content type='text'>
Move these to the amdgpu directory to match what we
do for other asics.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove detect_hw_virtualization interface</title>
<updated>2017-01-27T16:13:05Z</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-01-09T03:53:14Z</published>
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<id>urn:sha1:c8394f38fa2362385fd34f7034a2276b458c640e</id>
<content type='text'>
Call detection function driectly, so remove the interface.

V2: ci and si also need to call the detect function.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Monk Liu &lt;monk.liu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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