user/sven/linux.git/drivers/gpu/drm/amd/amdgpu/si.c, branch v5.10.67

drm/amd/amdgpu: fix comparison pointer to bool warning in si.c

2020-09-15T21:52:43Z

Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/si.c:1342:5-10: WARNING: Comparison to bool Acked-by: Christian König Signed-off-by: Zheng Bin Signed-off-by: Alex Deucher

drm/amdgpu: add pre_asic_init callback for SI

2020-08-26T20:40:18Z

Nothing to do for this family. Acked-by: Nirmoy Das Signed-off-by: Alex Deucher

drm/amdgpu: note what type of reset we are using

2020-08-14T21:03:20Z

When we reset the GPU, note what type of reset will be used. This makes debugging different reset scenarios more clear as the driver may use different reset methods depending on conditions on the system. Acked-by: Nirmoy Das Signed-off-by: Alex Deucher

drm/amdgpu/si: initial support for GPU reset

2020-07-28T13:22:57Z

Ported from radeon. Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: enable DC support for SI parts (v2)

2020-07-28T13:22:48Z

[Why] amdgpu_device.c requires changes for SI chipsets support si.c require changes for Display Manager IP block enabling [How] amdgpu_device.c: add SI families in amdgpu_device_asic_has_dc_support() si.c: changes in si_set_ip_blocks() for Display Manager IP blocks enablement (v1) NOTE: As per Kaveri and older amdgpu.dc=1 kernel cmdline is required (v2) fix for bc011f9350 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence") remove CHIP_HAINAN support since it does not have physical DCE6 module Reviewed-by: Alex Deucher Signed-off-by: Mauro Rossi Signed-off-by: Alex Deucher

drm/amdgpu: add module parameter choose reset mode

2020-07-15T16:42:01Z

Default value is auto, doesn't change original reset method logic. v2: change to use parameter reset_method v3: add warn msg if specified mode isn't supported Signed-off-by: Likun Gao Signed-off-by: Wenhui Sheng Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: SI support for VCE clock control

2020-07-02T16:02:49Z

Port functionality from the Radeon driver to support VCE clock control. Signed-off-by: Alex Jivin Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: SI support for UVD clock control

2020-07-02T16:02:49Z

Port functionality from the Radeon driver to support UVD clock control. Signed-off-by: Alex Jivin Reviewed-by: Alex Deucher Acked-by: Christian König Signed-off-by: Alex Deucher

drm amdgpu: SI UVD enabled on Verde, Tahiti, Pitcairn

2020-07-01T05:59:24Z

Enable asic Verde, Tahiti and Pitcairn UVD block. Signed-off-by: Sonny Jiang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm amdgpu: SI UVD enable for Oland

2020-07-01T05:59:24Z

Enable Oland UVD block. Signed-off-by: Sonny Jiang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher