<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/gpu/drm/amd/include, branch v4.9.53</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.9.53</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.9.53'/>
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<updated>2016-10-14T15:51:04Z</updated>
<entry>
<title>drm/amdgpu: fix amdgpu_need_full_reset (v2)</title>
<updated>2016-10-14T15:51:04Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-10-13T20:07:03Z</published>
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<id>urn:sha1:da146d3b5262c1866c868b9dec1bd0f834d6ded6</id>
<content type='text'>
IP types are not an index.  Each asic may have number and
type of IPs.  Properly check the the type rather than
using the type id as an index.

v2: fix all the IPs to not use IP type as an idx as well.

Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu:add fw version entry to info</title>
<updated>2016-09-22T14:24:15Z</updated>
<author>
<name>Frank Min</name>
<email>Frank.Min@amd.com</email>
</author>
<published>2016-04-27T10:53:29Z</published>
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<id>urn:sha1:fc76cbf45651f58284b8035ae1938e8ff5d19ee7</id>
<content type='text'>
Signed-off-by: Frank Min &lt;Frank.Min@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement raster configuration for gfx v6</title>
<updated>2016-09-19T18:38:24Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2016-09-09T08:37:08Z</published>
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<id>urn:sha1:865ab832ba78a1baf03fed90dccf5088e63a3aa3</id>
<content type='text'>
This patch is to implement the raster configuration and harvested
configuration of gfx v6.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Edward O'Callaghan &lt;funfunctor@folklore1984.net&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add si dpm support in amdgpu_atombios</title>
<updated>2016-08-31T19:21:07Z</updated>
<author>
<name>Maruthi Srinivas Bayyavarapu</name>
<email>Maruthi.Bayyavarapu@amd.com</email>
</author>
<published>2016-04-26T14:54:38Z</published>
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<id>urn:sha1:9139d731fdaa52b85543f2713d65ca860e0ce884</id>
<content type='text'>
v2: renamed _atom_ to _atombios_ for consistency
    added ulClockParams to _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 and
    _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 to avoid build break

Signed-off-by: Maruthi Bayyavarapu &lt;maruthi.bayyavarapu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add si implementation v10</title>
<updated>2016-08-31T16:11:19Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T06:08:49Z</published>
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<id>urn:sha1:62a37553414a344491c64e8fd89577dcc1b8bcbb</id>
<content type='text'>
v5: rebase fixes
v6: add mgcg arrays
v7: rebase fixes
v8: rebase fixes
v9: add get_disabled_bios(), make get_xclk static
v10: fix oland and hainan asic specific handle at si_program_aspm

Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add DMA implementation for si v8</title>
<updated>2016-08-31T16:10:51Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T06:05:23Z</published>
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<id>urn:sha1:30d1574fa4c71cf390ae4af57585a850612db8f7</id>
<content type='text'>
v4: rebase fixes
v5: use the generic nop fill
v6: rebase fixes
v7: rebase fixes
    copy count fixes from Jonathan
    general cleanup
    add fill buffer implementation
v8: adapt write_pte and copy_pte to latest changes

Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add display controller implementation for si v10</title>
<updated>2016-08-31T16:10:19Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T06:03:24Z</published>
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<id>urn:sha1:e2cdf640cbb5b7d6643e1c8ad54bf3bfc99d4d48</id>
<content type='text'>
v4: rebase fixups
v5: more fixes based on dce8 code
v6: squash in dmif offset fix
v7: rebase fixups
v8: rebase fixups, drop some debugging remnants
v9: fix BE build
v10: include Marek's tiling fixes, add support for
     page_flip_target, set MASTER_UDPATE_MODE=0,
     fix cursor

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add si header files v4</title>
<updated>2016-08-31T16:09:08Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T05:53:10Z</published>
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<id>urn:sha1:0f27e46258ee73e2fd149f91cb176475ce9b7537</id>
<content type='text'>
v4: drop unused DCE6 macro

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add SI asics types v2</title>
<updated>2016-08-30T22:02:02Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-21T09:00:06Z</published>
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<id>urn:sha1:26d721c5f5f1d2b140c6df5a361dcebc8cbf090b</id>
<content type='text'>
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add support for getting sub_device id and</title>
<updated>2016-08-25T16:23:00Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2016-08-22T12:48:13Z</published>
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<id>urn:sha1:2fef37c62cb6338ca15b30b05ec91b8bcc7b7dbe</id>
<content type='text'>
sub_vendor_id in cgs interface.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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