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<title>user/sven/linux.git/drivers/gpu/drm/amd, branch v4.10.3</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.10.3</id>
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<updated>2017-03-15T02:20:15Z</updated>
<entry>
<title>Revert "drm/amdgpu: update tile table for oland/hainan"</title>
<updated>2017-03-15T02:20:15Z</updated>
<author>
<name>Jean Delvare</name>
<email>jdelvare@suse.de</email>
</author>
<published>2017-03-02T17:21:35Z</published>
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<id>urn:sha1:0f9e6fc5b76df7e9c123cdd2690abfd59486a1d0</id>
<content type='text'>
Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for
oland/hainan") as it is causing ugly visual artifacts on at least
Oland. This is only an optimization so we can live without it.

This fixes kernel bug #194761:
amdgpu driver breaks on Oland (SI)
https://bugzilla.kernel.org/show_bug.cgi?id=194761

Signed-off-by: Jean Delvare &lt;jdelvare@suse.de&gt;
Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
Cc: Flora Cui &lt;Flora.Cui@amd.com&gt;
Cc: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/pm: check for headless before calling compute_clocks</title>
<updated>2017-03-15T02:20:14Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-02-10T23:09:32Z</published>
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<id>urn:sha1:2deaea3e0d07fc9e3ab41e7c6f4d63b85f0fcdbb</id>
<content type='text'>
commit c10c8f7c27103bd7ac02d041d9d6e97296d48fc1 upstream.

Don't update display bandwidth on headless asics.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=99387

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>drm/amdgpu: add more cases to DCE11 possible crtc mask setup</title>
<updated>2017-03-15T02:20:14Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-02-10T05:00:52Z</published>
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<id>urn:sha1:33d129a09aae8b0f87b49702c96b365fe9d9128d</id>
<content type='text'>
commit 4ce3bd45b351633f2a0512c587f7fcba2ce044e8 upstream.

Add cases for asics with 3 and 5 crtcs.  Fixes an artificial
limitation on asics with 3 or 5 crtcs.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=99744

Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>drm/amdgpu/si: fix crash on headless asics</title>
<updated>2017-02-02T16:13:50Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-01-27T15:31:52Z</published>
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<id>urn:sha1:57bcd0a6364cd4eaa362d7ff1777e88ddf501602</id>
<content type='text'>
Missing check for crtcs present.

Fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=193341
https://bugs.freedesktop.org/show_bug.cgi?id=99387

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix unload driver issue for virtual display</title>
<updated>2017-01-23T21:47:18Z</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-01-19T01:57:41Z</published>
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<id>urn:sha1:3a1d19a29670aa7eb58576a31883d0aa9fb77549</id>
<content type='text'>
Virtual display doesn't allocate amdgpu_encoder when initializing,
so will get invaild pointer if try to free amdgpu_encoder when
unloading driver.

Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: check ring being ready before using</title>
<updated>2017-01-23T21:47:01Z</updated>
<author>
<name>Ding Pixel</name>
<email>pding@amd.com</email>
</author>
<published>2017-01-18T09:26:38Z</published>
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<id>urn:sha1:c5f21c9f878b8dcd54d0b9739c025ca73cb4c091</id>
<content type='text'>
Return success when the ring is properly initialized, otherwise return
failure.

Tonga SRIOV VF doesn't have UVD and VCE engines, the initialization of
these IPs is bypassed. The system crashes if application submit IB to
their rings which are not ready to use. It could be a common issue if
IP having ring buffer is disabled for some reason on specific ASIC, so
it should check the ring being ready to use.

Bug: amdgpu_test crashes system on Tonga VF.

Signed-off-by: Ding Pixel &lt;Pixel.Ding@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add support for new hainan variants</title>
<updated>2017-01-17T20:25:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-01-17T20:06:58Z</published>
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<id>urn:sha1:17324b6add82d6c0bf119f1d1944baef392a4e39</id>
<content type='text'>
New hainan parts require updated smc firmware.

Cc: Sonny Jiang &lt;sonny.jiang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: change clock gating mode for uvd_v4.</title>
<updated>2017-01-17T20:25:26Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-01-12T13:48:26Z</published>
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<id>urn:sha1:ca581e45335c6aa45e5b27999bc13bdefb7e84d9</id>
<content type='text'>
use sw cg when decode. and hw cg when idle.

fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=99313
https://bugzilla.kernel.org/show_bug.cgi?id=192161

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Ack-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix program vce instance logic error.</title>
<updated>2017-01-17T20:25:04Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-01-10T12:03:59Z</published>
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<id>urn:sha1:50a1ebc70a2803deb7811fc73fb55d70e353bc34</id>
<content type='text'>
need to clear bit31-29 in GRBM_GFX_INDEX,
then the program can be valid.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix bug set incorrect value to vce register</title>
<updated>2017-01-17T20:24:55Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-01-10T12:00:40Z</published>
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<id>urn:sha1:e05208ded1905e500cd5b369d624b071951c68b9</id>
<content type='text'>
Set the proper bits for clockgating setup.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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