user/sven/linux.git/drivers/gpu/drm/panel, branch v4.4

spi: Drop owner assignment from spi_drivers

2015-10-28T01:30:17Z

An spi_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Andrew F. Davis Acked-by: Jonathan Cameron Signed-off-by: Mark Brown

drm/panel: Add support for LG LG4573 480x800 4.3" panel

2015-08-14T19:35:35Z

The LG4573 is used on the LG LCD LB043WV2-SD01, an industrial 4.3" TFT panel with SPI control interface. Signed-off-by: Heiko Schocher Signed-off-by: Thierry Reding

drm/panel: Add display timing for Okaya RS800480T-7X0GP

2015-08-14T19:35:35Z

Add support for the Okaya RS800480T-7X0GP to the DRM simple panel driver. The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel LCD interface. It supports pixel clocks in the range of 30-40 MHz. This panel details can be found at: http://boundarydevices.com/product/7-800x480-display/ Signed-off-by: Gary Bisson Signed-off-by: Thierry Reding

drm/panel: simple: Add support for NEC NL4827HC19-05B 480x272 panel

2015-08-14T19:35:33Z

This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM simple panel driver. Signed-off-by: Alison Wang Signed-off-by: Xiubo Li Signed-off-by: Jianwei Wang Acked-by: Daniel Vetter [treding@nvidia.com: add .bpc field for panel] Signed-off-by: Thierry Reding

drm/panel: simple: Add support for AUO B080UAN01

2015-08-14T19:35:33Z

The AUO B080UAN01 is an 8.0" WUXGA TFT LCD panel connected using four DSI lanes. It can be supported by the simple-panel driver. Signed-off-by: Thierry Reding

drm/panel: simple: Correct minimum hsync length of the HannStar HSD070PWW1 panel

2015-08-14T19:35:32Z

According to the data sheet, the minimum horizontal blanking interval is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the minimum working horizontal blanking interval to be 60 clocks. Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach Signed-off-by: Thierry Reding

drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel

2015-08-14T19:35:31Z

The bus format both specifies the bpc and the way the individual bits get serialized into the 7 LVDS timeslots. While the is only one standard mapping for 6 bpc and so the driver could infer the bit mapping from the bpc alone, there are more options for the 8 bpc case which makes specifiying the bus format mandatory. To keep things consistent across panels and to set a precedent for new panel additions add the proper bus format. Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach Signed-off-by: Thierry Reding

drm/panel: Add Samsung prefix to panel drivers

2015-08-13T12:33:52Z

The likelihood of getting a large number of panel drivers from different vendors is quite high. Add a prefix to the two existing Samsung panel drivers to set a guideline for future patch submissions. Using vendor prefixes consistently should allow a cleaner organization of the tree. Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding

drm/panel: simple: Add bus format for HannStar HSD100PXN1

2015-06-12T14:40:42Z

This patch adds the bus_format field to the HSD100PXN1 panel structure. Signed-off-by: Philipp Zabel Signed-off-by: Thierry Reding

drm/panel: simple: Add display timing for HannStar HSD100PXN1

2015-06-12T14:40:35Z

Add support for the Hannstar HSD100PXN1 to the DRM simple panel driver. The HSD100PXN1 is an XGA (1024x768) panel with an 18-bit LVDS interface. It supports pixel clocks in the range of 55-75 MHz. This panel is offered for sale by Freescale as a companion part to its' i.MX5x Quick Start board and i.MX6 SABRE platforms with under the name MCIMX-LVDS1. Signed-off-by: Eric Nelson Signed-off-by: Thierry Reding