<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/gpu/host1x, branch v4.4.261</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.4.261</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.4.261'/>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/'/>
<updated>2018-11-10T15:41:39Z</updated>
<entry>
<title>gpu: host1x: fix error return code in host1x_probe()</title>
<updated>2018-11-10T15:41:39Z</updated>
<author>
<name>Gustavo A. R. Silva</name>
<email>gustavo@embeddedor.com</email>
</author>
<published>2017-08-08T05:08:06Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=b99152a593de5df769c889177e731565845aefbd'/>
<id>urn:sha1:b99152a593de5df769c889177e731565845aefbd</id>
<content type='text'>
[ Upstream commit 7b2c63de20080c18d0de35b292ad61fc9bc8328e ]

platform_get_irq() returns an error code, but the host1x driver
ignores it and always returns -ENXIO. This is not correct and,
prevents -EPROBE_DEFER from being propagated properly.

Notice that platform_get_irq() no longer returns 0 on error:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e330b9a6bb35dc7097a4f02cb1ae7b6f96df92af

Print and propagate the return value of platform_get_irq on failure.

This issue was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva &lt;gustavo@embeddedor.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Fix MLOCK's debug info</title>
<updated>2015-10-02T12:40:12Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2015-06-28T19:27:02Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=3fe2c7d4c85b4557c9772ff16f31ddc18cfd2521'/>
<id>urn:sha1:3fe2c7d4c85b4557c9772ff16f31ddc18cfd2521</id>
<content type='text'>
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-By: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Power down regulators when unused</title>
<updated>2015-08-13T11:47:21Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-10T09:29:41Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=15372d4be7f099662dc84e4e35e844bd4373d959'/>
<id>urn:sha1:15372d4be7f099662dc84e4e35e844bd4373d959</id>
<content type='text'>
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Add Tegra210 support</title>
<updated>2015-08-13T11:47:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:23:20Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=5e7752436e10427ba598de4f2f6b7889daf586cc'/>
<id>urn:sha1:5e7752436e10427ba598de4f2f6b7889daf586cc</id>
<content type='text'>
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Add Tegra132 support</title>
<updated>2015-08-13T11:47:19Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:20:32Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=7fd3ecad3f768fd2b39fc4db12044437fbf5d735'/>
<id>urn:sha1:7fd3ecad3f768fd2b39fc4db12044437fbf5d735</id>
<content type='text'>
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Constify OF match table</title>
<updated>2015-08-13T11:47:18Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:19:19Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=c22fb79099dbec82b8280106c43f6e800ecc854c'/>
<id>urn:sha1:c22fb79099dbec82b8280106c43f6e800ecc854c</id>
<content type='text'>
This table is never modified and can therefore reside in read-only
memory.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Clear calibration status</title>
<updated>2015-08-13T11:47:17Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:17:44Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=2ed264bf916b689fe0c71ac726995f0876062667'/>
<id>urn:sha1:2ed264bf916b689fe0c71ac726995f0876062667</id>
<content type='text'>
Before starting a new calibration cycle, make sure to clear the current
status by writing a 1 to the various "calibration done" bits.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Fix clock lane register for DSI</title>
<updated>2015-08-13T11:47:16Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:06:08Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=8ed5c0623272663783e052123fea02651464a0a5'/>
<id>urn:sha1:8ed5c0623272663783e052123fea02651464a0a5</id>
<content type='text'>
Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Parameterize to support future SoCs</title>
<updated>2015-08-13T11:47:15Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:03:49Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=83a3c223cc5678c5ced554fa2819747fd53437c7'/>
<id>urn:sha1:83a3c223cc5678c5ced554fa2819747fd53437c7</id>
<content type='text'>
Parameterize more of the register programming to accomodate for changes
required by future SoC generations.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Export host1x_syncpt_read()</title>
<updated>2015-04-02T16:46:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-01-28T13:29:02Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=b4a20144e0c0a45431695fa5968ce2ed8c9ce6ca'/>
<id>urn:sha1:b4a20144e0c0a45431695fa5968ce2ed8c9ce6ca</id>
<content type='text'>
This function is used to read the current value of the syncpt and is
useful in situations where drivers don't schedule work and wait for the
syncpoint to increment. One particular use-case is using the syncpoint
as a VBLANK counter.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
