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<title>user/sven/linux.git/drivers/gpu/host1x, branch v4.4.63</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2015-10-02T12:40:12Z</updated>
<entry>
<title>gpu: host1x: Fix MLOCK's debug info</title>
<updated>2015-10-02T12:40:12Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2015-06-28T19:27:02Z</published>
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<id>urn:sha1:3fe2c7d4c85b4557c9772ff16f31ddc18cfd2521</id>
<content type='text'>
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-By: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Power down regulators when unused</title>
<updated>2015-08-13T11:47:21Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-10T09:29:41Z</published>
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<id>urn:sha1:15372d4be7f099662dc84e4e35e844bd4373d959</id>
<content type='text'>
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Add Tegra210 support</title>
<updated>2015-08-13T11:47:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:23:20Z</published>
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<id>urn:sha1:5e7752436e10427ba598de4f2f6b7889daf586cc</id>
<content type='text'>
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Add Tegra132 support</title>
<updated>2015-08-13T11:47:19Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:20:32Z</published>
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<id>urn:sha1:7fd3ecad3f768fd2b39fc4db12044437fbf5d735</id>
<content type='text'>
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Constify OF match table</title>
<updated>2015-08-13T11:47:18Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:19:19Z</published>
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<id>urn:sha1:c22fb79099dbec82b8280106c43f6e800ecc854c</id>
<content type='text'>
This table is never modified and can therefore reside in read-only
memory.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Clear calibration status</title>
<updated>2015-08-13T11:47:17Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:17:44Z</published>
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<id>urn:sha1:2ed264bf916b689fe0c71ac726995f0876062667</id>
<content type='text'>
Before starting a new calibration cycle, make sure to clear the current
status by writing a 1 to the various "calibration done" bits.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Fix clock lane register for DSI</title>
<updated>2015-08-13T11:47:16Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:06:08Z</published>
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<id>urn:sha1:8ed5c0623272663783e052123fea02651464a0a5</id>
<content type='text'>
Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Parameterize to support future SoCs</title>
<updated>2015-08-13T11:47:15Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-04-08T15:03:49Z</published>
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<id>urn:sha1:83a3c223cc5678c5ced554fa2819747fd53437c7</id>
<content type='text'>
Parameterize more of the register programming to accomodate for changes
required by future SoC generations.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Export host1x_syncpt_read()</title>
<updated>2015-04-02T16:46:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2015-01-28T13:29:02Z</published>
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<id>urn:sha1:b4a20144e0c0a45431695fa5968ce2ed8c9ce6ca</id>
<content type='text'>
This function is used to read the current value of the syncpt and is
useful in situations where drivers don't schedule work and wait for the
syncpoint to increment. One particular use-case is using the syncpoint
as a VBLANK counter.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Provide a proper struct bus_type</title>
<updated>2015-01-27T09:09:14Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-18T14:29:14Z</published>
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<id>urn:sha1:f4c5cf88fbd50e4779042268947b2e2f90c20484</id>
<content type='text'>
Previously the struct bus_type exported by the host1x infrastructure was
only a very basic skeleton. Turn that implementation into a more full-
fledged bus to support proper probe ordering and power management.

Note that the bus infrastructure needs to be available before any of the
drivers can be registered. This is automatically ensured if all drivers
are built as loadable modules (via symbol dependencies). If all drivers
are built-in there are no such guarantees and the link order determines
the initcall ordering. Adjust drivers/gpu/Makefile to make sure that the
host1x bus infrastructure is initialized prior to any of its users (only
drm/tegra currently).

v2: Fix building host1x and tegra-drm as modules
    Reported-by: Dave Airlie &lt;airlied@gmail.com&gt;

Reviewed-by: Sean Paul &lt;seanpaul@chromium.org&gt;
Reviewed-by: Mark Zhang &lt;markz@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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