user/sven/linux.git/drivers/gpu/host1x, branch v4.5.2Linux Kernel
https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.5.22016-03-04T15:24:57Zgpu: host1x: Set DMA ops on device creation2016-03-04T15:24:57ZAlexandre Courbotacourbot@nvidia.com2016-02-26T09:06:53Zurn:sha1:c95469aa5a188384ccf8ac520ece931c66caf8aa
Currently host1x-instanciated devices have their dma_ops left to NULL,
which makes any DMA operation (like buffer import) on ARM64 fallback
to the dummy_dma_ops and fail with an error.
This patch calls of_dma_configure() with the host1x node when creating
such a device, so the proper DMA operations are set.
Suggested-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Set DMA mask2016-03-04T15:24:56ZAlexandre Courbotacourbot@nvidia.com2016-02-26T09:06:52Zurn:sha1:097452e61366a939a4772332181cea7cdcc74760
The default DMA mask covers a 32 bits address range, but host1x devices
can address a larger range on TK1 and TX1. Set the DMA mask to the range
addressable when we use the IOMMU to prevent the use of bounce buffers.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Add Tegra210 support2015-12-14T09:50:33ZThierry Redingtreding@nvidia.com2015-03-23T09:46:28Zurn:sha1:a134789a67480e6cc7e50c9dfcbc7adca5016010
The host1x unit found in Tegra210 SoCs is very similar to the unit in
Tegra124, but it has 2 additional channels for a total of 14 channels.
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Remove core driver on unregister2015-12-14T09:50:33ZThierry Redingtreding@nvidia.com2015-08-24T12:51:04Zurn:sha1:e3e70814cebb0beec47dd38e60f89850950a2903
When unregistering a host1x driver, make sure to unregister the core
driver as well to prevent it from sticking around and oppose reloading
of the driver.
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Use platform_register/unregister_drivers()2015-12-14T09:50:32ZThierry Redingtreding@nvidia.com2015-12-02T16:24:20Zurn:sha1:28fae81f93d5482f25bb8e9881104ad1157c2cfd
These new helpers simplify implementing multi-driver modules and
properly handle failure to register one driver by unregistering all
previously registered drivers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Fix MLOCK's debug info2015-10-02T12:40:12ZDmitry Osipenkodigetx@gmail.com2015-06-28T19:27:02Zurn:sha1:3fe2c7d4c85b4557c9772ff16f31ddc18cfd2521
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-By: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Power down regulators when unused2015-08-13T11:47:21ZThierry Redingtreding@nvidia.com2015-04-10T09:29:41Zurn:sha1:15372d4be7f099662dc84e4e35e844bd4373d959
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Add Tegra210 support2015-08-13T11:47:20ZThierry Redingtreding@nvidia.com2015-04-08T15:23:20Zurn:sha1:5e7752436e10427ba598de4f2f6b7889daf586cc
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Add Tegra132 support2015-08-13T11:47:19ZThierry Redingtreding@nvidia.com2015-04-08T15:20:32Zurn:sha1:7fd3ecad3f768fd2b39fc4db12044437fbf5d735
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: mipi: Constify OF match table2015-08-13T11:47:18ZThierry Redingtreding@nvidia.com2015-04-08T15:19:19Zurn:sha1:c22fb79099dbec82b8280106c43f6e800ecc854c
This table is never modified and can therefore reside in read-only
memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>