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<title>user/sven/linux.git/drivers/gpu/ipu-v3, branch v5.10.245</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2023-03-11T15:39:30Z</updated>
<entry>
<title>gpu: ipu-v3: common: Add of_node_put() for reference returned by of_graph_get_port_by_id()</title>
<updated>2023-03-11T15:39:30Z</updated>
<author>
<name>Liang He</name>
<email>windhl@126.com</email>
</author>
<published>2022-07-20T15:22:27Z</published>
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<id>urn:sha1:8eb74bd9c9726425fe62330a2eda4d862edb6dd1</id>
<content type='text'>
[ Upstream commit 9afdf98cfdfa2ba8ec068cf08c5fcdc1ed8daf3f ]

In ipu_add_client_devices(), we need to call of_node_put() for
reference returned by of_graph_get_port_by_id() in fail path.

Fixes: 17e052175039 ("gpu: ipu-v3: Do not bail out on missing optional port nodes")
Signed-off-by: Liang He &lt;windhl@126.com&gt;
Reviewed-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Link: https://lore.kernel.org/r/20220720152227.1288413-1-windhl@126.com
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20220720152227.1288413-1-windhl@126.com
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Fix dev_dbg frequency output</title>
<updated>2022-04-20T07:23:22Z</updated>
<author>
<name>Leo Ruan</name>
<email>tingquan.ruan@cn.bosch.com</email>
</author>
<published>2022-02-07T15:14:11Z</published>
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<id>urn:sha1:aa8cdedaf7606fc0e7e16cdf67c1d651f2c93b5f</id>
<content type='text'>
[ Upstream commit 070a88fd4a03f921b73a2059e97d55faaa447dab ]

This commit corrects the printing of the IPU clock error percentage if
it is between -0.1% to -0.9%. For example, if the pixel clock requested
is 27.2 MHz but only 27.0 MHz can be achieved the deviation is -0.8%.
But the fixed point math had a flaw and calculated error of 0.2%.

Before:
  Clocks: IPU 270000000Hz DI 24716667Hz Needed 27200000Hz
  IPU clock can give 27000000 with divider 10, error 0.2%
  Want 27200000Hz IPU 270000000Hz DI 24716667Hz using IPU, 27000000Hz

After:
  Clocks: IPU 270000000Hz DI 24716667Hz Needed 27200000Hz
  IPU clock can give 27000000 with divider 10, error -0.8%
  Want 27200000Hz IPU 270000000Hz DI 24716667Hz using IPU, 27000000Hz

Signed-off-by: Leo Ruan &lt;tingquan.ruan@cn.bosch.com&gt;
Signed-off-by: Mark Jonas &lt;mark.jonas@de.bosch.com&gt;
Reviewed-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Link: https://lore.kernel.org/r/20220207151411.5009-1-mark.jonas@de.bosch.com
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Fix i.MX IPU-v3 offset calculations for (semi)planar U/V formats</title>
<updated>2021-09-08T06:49:00Z</updated>
<author>
<name>Krzysztof Hałasa</name>
<email>khalasa@piap.pl</email>
</author>
<published>2021-06-07T10:49:07Z</published>
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<id>urn:sha1:9872349b088d5a94ccbe23c2ded8820b5a082cea</id>
<content type='text'>
[ Upstream commit 7cca7c8096e2c8a4149405438329b5035d0744f0 ]

Video captured in 1400x1050 resolution (bytesperline aka stride = 1408
bytes) is invalid. Fix it.

Signed-off-by: Krzysztof Halasa &lt;khalasa@piap.pl&gt;
Link: https://lore.kernel.org/r/m3y2bmq7a4.fsf@t19.piap.pl
[p.zabel@pengutronix.de: added "gpu: ipu-v3:" prefix to commit description]
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: remove unused functions</title>
<updated>2020-10-26T09:42:38Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-07-29T12:26:15Z</published>
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<id>urn:sha1:58b24a38f0deac253ba9c5be128e3da6a86041ad</id>
<content type='text'>
ipu_mbus_code_to_colorspace, ipu_stride_to_bytes, and
ipu_pixelformat_is_planar are unused. Remove them.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Reviewed-by: Sam Ravnborg &lt;sam@ravnborg.org&gt;
</content>
</entry>
<entry>
<title>treewide: Use fallthrough pseudo-keyword</title>
<updated>2020-08-23T22:36:59Z</updated>
<author>
<name>Gustavo A. R. Silva</name>
<email>gustavoars@kernel.org</email>
</author>
<published>2020-08-23T22:36:59Z</published>
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<id>urn:sha1:df561f6688fef775baa341a0f5d960becd248b11</id>
<content type='text'>
Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
fall-through markings when it is the case.

[1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through

Signed-off-by: Gustavo A. R. Silva &lt;gustavoars@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: Wait for all EOFs before completing a tile</title>
<updated>2020-07-20T13:16:05Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2020-06-25T18:13:37Z</published>
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<id>urn:sha1:dd81d821d0b3f77d949d0cac5c05c1f05b921d46</id>
<content type='text'>
Use a bit-mask of EOF irqs to determine when all required idmac
channel EOFs have been received for a tile conversion, and only do
tile completion processing after all EOFs have been received. Otherwise
it was found that a conversion would stall after the completion of a
tile and the start of the next tile, because the input/read idmac
channel had not completed and entered idle state, thus locking up the
channel when attempting to re-start it for the next tile.

Fixes: 0537db801bb01 ("gpu: ipu-v3: image-convert: reconfigure IC per tile")
Signed-off-by: Steve Longerbeam &lt;slongerbeam@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: Combine rotate/no-rotate irq handlers</title>
<updated>2020-07-20T13:16:05Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2020-06-17T22:40:37Z</published>
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<id>urn:sha1:0f6245f42ce9b7e4d20f2cda8d5f12b55a44d7d1</id>
<content type='text'>
Combine the rotate_irq() and norotate_irq() handlers into a single
eof_irq() handler.

Signed-off-by: Steve Longerbeam &lt;slongerbeam@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Restore RGB32, BGR32</title>
<updated>2020-07-20T13:16:05Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2020-06-17T22:40:36Z</published>
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<id>urn:sha1:22b2cfad752d4b278ea7c38c0ee961ca50198ce8</id>
<content type='text'>
RGB32 and BGR32 formats were inadvertently removed from the switch
statement in ipu_pixelformat_to_colorspace(). Restore them.

Fixes: a59957172b0c ("gpu: ipu-v3: enable remaining 32-bit RGB V4L2 pixel formats")
Signed-off-by: Steve Longerbeam &lt;slongerbeam@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: only sample into the next tile if necessary</title>
<updated>2019-08-19T14:25:30Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-14T08:53:30Z</published>
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<id>urn:sha1:4d24376370fbfc87231d54434a683f2913abcce4</id>
<content type='text'>
The first pixel of the next tile is only sampled by the hardware if the
fractional input position corresponding to the last written output pixel
is not an integer position.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: move tile burst alignment out of loop</title>
<updated>2019-08-19T14:25:30Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-14T08:50:13Z</published>
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<id>urn:sha1:fbefb84dd142c7d75232ae9d446ae36829c2dc97</id>
<content type='text'>
Burst aligned input and output width can be calculated once per column,
instead of repeatedly for each tile in the column. The same goes for
input and output height per row. Also don't round up the same values
repeatedly.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
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