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<title>user/sven/linux.git/drivers/gpu/ipu-v3, branch v5.4.108</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.4.108</id>
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<updated>2020-08-21T11:05:32Z</updated>
<entry>
<title>gpu: ipu-v3: image-convert: Wait for all EOFs before completing a tile</title>
<updated>2020-08-21T11:05:32Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2020-06-25T18:13:37Z</published>
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<id>urn:sha1:386f82040c84728c7c058f34cdd7113c2f4c5b16</id>
<content type='text'>
[ Upstream commit dd81d821d0b3f77d949d0cac5c05c1f05b921d46 ]

Use a bit-mask of EOF irqs to determine when all required idmac
channel EOFs have been received for a tile conversion, and only do
tile completion processing after all EOFs have been received. Otherwise
it was found that a conversion would stall after the completion of a
tile and the start of the next tile, because the input/read idmac
channel had not completed and entered idle state, thus locking up the
channel when attempting to re-start it for the next tile.

Fixes: 0537db801bb01 ("gpu: ipu-v3: image-convert: reconfigure IC per tile")
Signed-off-by: Steve Longerbeam &lt;slongerbeam@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: Combine rotate/no-rotate irq handlers</title>
<updated>2020-08-21T11:05:32Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2020-06-17T22:40:37Z</published>
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<id>urn:sha1:0f77e95efd75eee36ba1c536f27d46c548a31e55</id>
<content type='text'>
[ Upstream commit 0f6245f42ce9b7e4d20f2cda8d5f12b55a44d7d1 ]

Combine the rotate_irq() and norotate_irq() handlers into a single
eof_irq() handler.

Signed-off-by: Steve Longerbeam &lt;slongerbeam@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: Restore RGB32, BGR32</title>
<updated>2020-08-19T06:16:13Z</updated>
<author>
<name>Steve Longerbeam</name>
<email>slongerbeam@gmail.com</email>
</author>
<published>2020-06-17T22:40:36Z</published>
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<id>urn:sha1:7e206d89e1c7cdc8b84b9b08aebbc363f7a9b4ad</id>
<content type='text'>
[ Upstream commit 22b2cfad752d4b278ea7c38c0ee961ca50198ce8 ]

RGB32 and BGR32 formats were inadvertently removed from the switch
statement in ipu_pixelformat_to_colorspace(). Restore them.

Fixes: a59957172b0c ("gpu: ipu-v3: enable remaining 32-bit RGB V4L2 pixel formats")
Signed-off-by: Steve Longerbeam &lt;slongerbeam@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: only sample into the next tile if necessary</title>
<updated>2019-08-19T14:25:30Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-14T08:53:30Z</published>
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<id>urn:sha1:4d24376370fbfc87231d54434a683f2913abcce4</id>
<content type='text'>
The first pixel of the next tile is only sampled by the hardware if the
fractional input position corresponding to the last written output pixel
is not an integer position.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: move tile burst alignment out of loop</title>
<updated>2019-08-19T14:25:30Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-14T08:50:13Z</published>
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<id>urn:sha1:fbefb84dd142c7d75232ae9d446ae36829c2dc97</id>
<content type='text'>
Burst aligned input and output width can be calculated once per column,
instead of repeatedly for each tile in the column. The same goes for
input and output height per row. Also don't round up the same values
repeatedly.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: bail on invalid tile sizes</title>
<updated>2019-08-19T14:25:30Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-13T12:39:50Z</published>
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<id>urn:sha1:5fb8b650cc1170f5e7a0f1a4ab3bb2042c007102</id>
<content type='text'>
If we managed to create tiles sized 0x0 because of a bug in the seam
calculation, return with an error message instead of letting the driver
run into a division by zero later. Also check for tile sizes that are
larger than supported by the hardware.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: fix image downsize coefficients and tiling calculation</title>
<updated>2019-08-19T14:25:30Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-13T11:42:58Z</published>
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<id>urn:sha1:de2564c70fcc1dfee89fff92eccba5a711a921cc</id>
<content type='text'>
This patch effectively reverts commit 912bbf7e9ca4 ("gpu: ipu-v3:
image-convert: Fix image downsize coefficients") and replaces it with a
different solution based on the preceding patches.

The previous fix tried to solve the problem of intermediate tile size
between IC downsizing and main processing sections not being limited to
1024 pixels by downsizing the input image to a smaller intermediate size
in the downsizing box filter. This causes unnecessary blurring,
especially for scaling factors close to 1.

Now that the seam position calculation makes sure that the 1024 pixel
intermediate tile size limit is not exceeded, calculate the number of
tiles from the maximum of intermediate size and output size and avoid
unnecessary downsizing.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: limit input seam position to hardware requirements</title>
<updated>2019-08-19T14:25:30Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-13T11:42:58Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=2e67a553e965b32a648c85fbe1c667fa440d6c92'/>
<id>urn:sha1:2e67a553e965b32a648c85fbe1c667fa440d6c92</id>
<content type='text'>
Limit the input seam position to an interval that guarantees the tile
size does not exceed 1024 pixels after the IC downsizing section and
that space is left for the next tile.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: fix output seam valid interval</title>
<updated>2019-08-19T14:24:37Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-13T12:30:25Z</published>
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<id>urn:sha1:82c3e948cc0fe7e01b39d437f7a58b197ebb422d</id>
<content type='text'>
This fixes a failure to determine any seam if the output size is
exactly 1024 multiplied by the number of tiles in a given direction.
In that case an empty interval out_start == out_end is being passed
to find_best_seam, which looks for a seam out_start &lt;= x &lt; out_end.

Also reduce the interval for all but the left column / top row, to
avoid returning position 0 as best fit.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>gpu: ipu-v3: image-convert: move output seam valid interval calculation into find_best_seam</title>
<updated>2019-08-19T14:22:21Z</updated>
<author>
<name>Philipp Zabel</name>
<email>p.zabel@pengutronix.de</email>
</author>
<published>2019-08-13T16:49:26Z</published>
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<id>urn:sha1:ca84b1b860407109b4b5f3802907f13bbef5d0fd</id>
<content type='text'>
This reduces code duplication and allows to apply the following
modifications in a single place.

Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
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