<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/iio/dac/Makefile, branch master</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2026-01-23T08:15:00Z</updated>
<entry>
<title>iio: dac: Add MAX22007 DAC driver support</title>
<updated>2026-01-23T08:15:00Z</updated>
<author>
<name>Janani Sunil</name>
<email>janani.sunil@analog.com</email>
</author>
<published>2026-01-19T11:24:24Z</published>
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<id>urn:sha1:f52690c50893ef1504990199c8a2dfbb869f38c6</id>
<content type='text'>
Add support for the MAX22007 4 channel DAC that drives a voltage or
current output on each channel.

Signed-off-by: Janani Sunil &lt;janani.sunil@analog.com&gt;
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: adding support for Microchip MCP47FEB02</title>
<updated>2025-12-31T17:59:18Z</updated>
<author>
<name>Ariana Lazar</name>
<email>ariana.lazar@microchip.com</email>
</author>
<published>2025-12-16T12:05:51Z</published>
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<id>urn:sha1:bf394cc8036989c9cc7d82ddede4c57e24912dc4</id>
<content type='text'>
This is the iio driver for Microchip MCP47F(E/V)B(0/1/2)1,
MCP47F(E/V)B(0/1/2)2, MCP47F(E/V)B(0/1/2)4 and MCP47F(E/V)B(0/1/2)8 series
of buffered voltage output Digital-to-Analog Converters with nonvolatile or
volatile memory and an I2C Interface.

The families support up to 8 output channels.

The devices can be 8-bit, 10-bit and 12-bit.

Signed-off-by: Ariana Lazar &lt;ariana.lazar@microchip.com&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@intel.com&gt;
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: ad5446: Separate I2C/SPI into different drivers</title>
<updated>2025-11-09T16:15:13Z</updated>
<author>
<name>Nuno Sá</name>
<email>nuno.sa@analog.com</email>
</author>
<published>2025-11-04T15:35:12Z</published>
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<id>urn:sha1:876d94024087b03494b206a5b5561fcd267824e7</id>
<content type='text'>
Properly separate the I2C and SPI drivers into two different drivers
living in their own source file (as usual). So that no need for the
hacky ifdefery.

Signed-off-by: Nuno Sá &lt;nuno.sa@analog.com&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@intel.com&gt;
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: ad3530r: Add driver for AD3530R and AD3531R</title>
<updated>2025-05-21T13:20:29Z</updated>
<author>
<name>Kim Seer Paller</name>
<email>kimseer.paller@analog.com</email>
</author>
<published>2025-04-29T02:19:18Z</published>
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<id>urn:sha1:93583174a3dffdcf604507106cb1d404bd65669d</id>
<content type='text'>
The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are
low-power, 16-bit, buffered voltage output DACs with software-
programmable gain controls, providing full-scale output spans of 2.5V or
5V for reference voltages of 2.5V. These devices operate from a single
2.7V to 5.5V supply and are guaranteed monotonic by design. The "R"
variants include a 2.5V, 5ppm/°C internal reference, which is disabled
by default.

Support for monitoring internal die temperature, output voltages, and
current of a selected channel via the MUXOUT pin using an external ADC
is currently not implemented.

Reviewed-by: David Lechner &lt;dlechner@baylibre.com&gt;
Signed-off-by: Kim Seer Paller &lt;kimseer.paller@analog.com&gt;
Reviewed-by: Andy Shevchenko &lt;andy@kernel.org&gt;
Link: https://patch.msgid.link/20250429-togreg-v7-3-0af9c543b545@analog.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: Support ROHM BD79703 DAC</title>
<updated>2024-12-28T14:28:14Z</updated>
<author>
<name>Matti Vaittinen</name>
<email>mazziesaccount@gmail.com</email>
</author>
<published>2024-12-19T11:39:37Z</published>
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<id>urn:sha1:af6aca656a85d250c3f39569266301035f023d23</id>
<content type='text'>
The ROHM BD79703 is a 6 channel digital to analog converter.

Based on the data-sheet examples the hardware would support setting the
DAC word without changing the actual output. The data-sheet is not too
specific on how the enabling the output of new voltage set by DAC
should be done - hence this is not implemented by the driver.

The BD79703 would also support two specific "PULL_DOWN" modes. These
aren't currently supported by the driver either.

Add a very basic support for controlling the channel outputs one-by-one.

Signed-off-by: Matti Vaittinen &lt;mazziesaccount@gmail.com&gt;
Link: https://patch.msgid.link/bc77d7b979ca28408a216f597082fcd94ec63be7.1734608215.git.mazziesaccount@gmail.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: ad3552r: add high-speed platform driver</title>
<updated>2024-11-03T20:33:32Z</updated>
<author>
<name>Angelo Dureghello</name>
<email>adureghello@baylibre.com</email>
</author>
<published>2024-10-28T21:45:34Z</published>
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<id>urn:sha1:0b4d9fe58be8260819c453fb4717f23bdafd3ba3</id>
<content type='text'>
Add High Speed ad3552r platform driver.

The ad3552r DAC is controlled by a custom (fpga-based) DAC IP
through the current AXI backend, or similar alternative IIO backend.

Compared to the existing driver (ad3552r.c), that is a simple SPI
driver, this driver is coupled with a DAC IIO backend that finally
controls the ad3552r by a fpga-based "QSPI+DDR" interface, to reach
maximum transfer rate of 33MUPS using dma stream capabilities.

All commands involving QSPI bus read/write are delegated to the backend
through the provided APIs for bus read/write.

Reviewed-by: Nuno Sa &lt;nuno.sa@analog.com&gt;
Signed-off-by: Angelo Dureghello &lt;adureghello@baylibre.com&gt;
Reviewed-by: David Lechner &lt;dlechner@baylibre.com&gt;
Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-7-f6960b4f9719@kernel-space.org
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: ad3552r: extract common code (no changes in behavior intended)</title>
<updated>2024-11-01T14:54:48Z</updated>
<author>
<name>Angelo Dureghello</name>
<email>adureghello@baylibre.com</email>
</author>
<published>2024-10-28T21:45:33Z</published>
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<id>urn:sha1:f665d7d33d7909cf51e2db0f0767ecab0295c0bd</id>
<content type='text'>
Extracting common code, to share common code to be used later
by the AXI driver version (ad3552r-axi.c).

Signed-off-by: Angelo Dureghello &lt;adureghello@baylibre.com&gt;
Reviewed-by: David Lechner &lt;dlechner@baylibre.com&gt;
Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-6-f6960b4f9719@kernel-space.org
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: support the ad8460 Waveform DAC</title>
<updated>2024-09-30T08:21:03Z</updated>
<author>
<name>Mariel Tinaco</name>
<email>Mariel.Tinaco@analog.com</email>
</author>
<published>2024-09-12T09:54:35Z</published>
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<id>urn:sha1:a976ef24c62540d6dd166a93e474684ae5463455</id>
<content type='text'>
The AD8460 is a “bits in, power out” high voltage, high-power,
high-speed driver optimized for large output current (up to ±1 A)
and high slew rate (up to ±1800 V/μs) at high voltage (up to ±40 V)
into capacitive loads.

A digital engine implements user-configurable features: modes for
digital input, programmable supply current, and fault monitoring
and programmable protection settings for output current,
output voltage, and junction temperature. The AD8460 operates on
high voltage dual supplies up to ±55 V and a single low voltage
supply of 5 V.

Signed-off-by: Mariel Tinaco &lt;Mariel.Tinaco@analog.com&gt;
Link: https://patch.msgid.link/20240912095435.18639-3-Mariel.Tinaco@analog.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: ltc2664: Add driver for LTC2664 and LTC2672</title>
<updated>2024-08-03T09:13:37Z</updated>
<author>
<name>Kim Seer Paller</name>
<email>kimseer.paller@analog.com</email>
</author>
<published>2024-07-18T05:18:34Z</published>
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<id>urn:sha1:4cc2fc445d2e4e63ed6bd5d310752d88d365f8e4</id>
<content type='text'>
LTC2664 4 channel, 12-/16-Bit Voltage Output SoftSpan DAC
LTC2672 5 channel, 12-/16-Bit Current Output Softspan DAC

Reviewed-by: Nuno Sa &lt;nuno.sa@analog.com&gt;
Co-developed-by: Michael Hennerich &lt;michael.hennerich@analog.com&gt;
Signed-off-by: Michael Hennerich &lt;michael.hennerich@analog.com&gt;
Signed-off-by: Kim Seer Paller &lt;kimseer.paller@analog.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://patch.msgid.link/20240718051834.32270-7-kimseer.paller@analog.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
<entry>
<title>iio: dac: support the ad9739a RF DAC</title>
<updated>2024-04-20T14:41:32Z</updated>
<author>
<name>Nuno Sa</name>
<email>nuno.sa@analog.com</email>
</author>
<published>2024-04-19T08:25:43Z</published>
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<id>urn:sha1:e77603d5468b9093c111a998a86604e21a9e7f48</id>
<content type='text'>
The AD9739A is a 14-bit, 2.5 GSPS high performance RF DACs that are capable
of synthesizing wideband signals from DC up to 3 GHz.

A dual-port, source synchronous, LVDS interface simplifies the digital
interface with existing FGPA/ASIC technology. On-chip controllers are used
to manage external and internal clock domain variations over temperature to
ensure reliable data transfer from the host to the DAC core.

Co-developed-by: Dragos Bogdan &lt;dragos.bogdan@analog.com&gt;
Signed-off-by: Dragos Bogdan &lt;dragos.bogdan@analog.com&gt;
Signed-off-by: Nuno Sa &lt;nuno.sa@analog.com&gt;
Link: https://lore.kernel.org/r/20240419-iio-backend-axi-dac-v4-10-5ca45b4de294@analog.com
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
</content>
</entry>
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