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<title>user/sven/linux.git/drivers/irqchip, branch next/master</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2026-04-17T11:59:55Z</updated>
<entry>
<title>Merge branch 'next' of git://git.kernel.org/pub/scm/virt/kvm/kvm.git</title>
<updated>2026-04-17T11:59:55Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@kernel.org</email>
</author>
<published>2026-04-17T11:59:49Z</published>
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<id>urn:sha1:3d2cd9a0633aec2b6412121a4c443176c12bd51e</id>
<content type='text'>
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</entry>
<entry>
<title>Merge branch 'soc_fsl' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux.git</title>
<updated>2026-04-17T11:41:20Z</updated>
<author>
<name>Mark Brown</name>
<email>broonie@kernel.org</email>
</author>
<published>2026-04-17T11:41:20Z</published>
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<id>urn:sha1:c64106e9ea2a1070f58d84ea5df1476abc8acfe4</id>
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<entry>
<title>Merge tag 'irq-msi-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2026-04-14T17:23:19Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-04-14T17:23:19Z</published>
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<id>urn:sha1:1d5e40351e7d521d7d143447d57315b6eb1e1160</id>
<content type='text'>
Pull MSI interrupt update from Thomas Gleixner:
 "A small update for the MSI interrupt library to check for callers
  which fail to provide the mandatory irq_write_msi_msg() callback,
  which prevents a NULL pointer dereference later"

* tag 'irq-msi-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/msi-lib: Refuse initialization when irq_write_msi_msg() is missing
</content>
</entry>
<entry>
<title>Merge tag 'irq-drivers-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2026-04-14T17:18:10Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-04-14T17:18:10Z</published>
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<id>urn:sha1:c0ecb2a9eeaa25832c1367ecc865ab2523b8c3d5</id>
<content type='text'>
Pull interrupt chip driver updates from Thomas Gleixner:

 - A large refactoring for the Renesas RZV2H driver to add new interrupt
   types cleanly

 - A large refactoring for the Renesas RZG2L driver to add support the
   new RZ/G3L variant

 - Add support for the new NXP S32N79 chip in the IMX irq-steer driver

 - Add support for the Apple AICv3 variant

 - Enhance the Loongson PCH LPC driver so it can be used on MIPS with
   device tree firmware

 - Allow the PIC32 EVIC driver to be built independent of MIPS in
   compile tests

 - The usual small fixes and enhancements all over the place

* tag 'irq-drivers-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (46 commits)
  irqchip/irq-pic32-evic: Add __maybe_unused for board_bind_eic_interrupt in COMPILE_TEST
  irqchip/renesas-rzv2h: Kill icu_err string
  irqchip/renesas-rzv2h: Kill swint_names[]
  irqchip/renesas-rzv2h: Kill swint_idx[]
  irqchip/renesas-rzg2l: Add NMI support
  irqchip/renesas-rzg2l: Clear the shared interrupt bit in rzg2l_irqc_free()
  irqchip/renesas-rzg2l: Replace raw_spin_{lock,unlock} with guard() in rzg2l_irq_set_type()
  irqchip/gic-v3: Print a warning for out-of-range interrupt numbers
  irqchip/renesas-rzg2l: Add shared interrupt support
  irqchip/renesas-rzg2l: Add RZ/G3L support
  irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro
  irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
  irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
  irqchip/renesas-rzg2l: Dynamically allocate fwspec array
  irqchip/renesas-rzg2l: Split rzfive_irqc_{mask,unmask} into separate IRQ and TINT handlers
  irqchip/renesas-rzg2l: Split rzfive_tint_irq_endisable() into separate IRQ and TINT helpers
  irqchip/renesas-rzg2l: Replace rzg2l_irqc_irq_{enable,disable} with TINT-specific handlers
  irqchip/renesas-rzg2l: Split set_type handler into separate IRQ and TINT functions
  irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT functions
  irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip instances
  ...
</content>
</entry>
<entry>
<title>Merge tag 'kvmarm-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD</title>
<updated>2026-04-13T09:49:54Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2026-04-13T09:49:54Z</published>
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<id>urn:sha1:e74c3a8891c05f88eeb87121de7e12dc95766a4a</id>
<content type='text'>
KVM/arm64 updates for 7.1

* New features:

- Add support for tracing in the standalone EL2 hypervisor code,
  which should help both debugging and performance analysis.
  This comes with a full infrastructure for 'remote' trace buffers
  that can be exposed by non-kernel entities such as firmware.

- Add support for GICv5 Per Processor Interrupts (PPIs), as the
  starting point for supporting the new GIC architecture in KVM.

- Finally add support for pKVM protected guests, with anonymous
  memory being used as a backing store. About time!

* Improvements and bug fixes:

- Rework the dreaded user_mem_abort() function to make it more
  maintainable, reducing the amount of state being exposed to
  the various helpers and rendering a substantial amount of
  state immutable.

- Expand the Stage-2 page table dumper to support NV shadow
  page tables on a per-VM basis.

- Tidy up the pKVM PSCI proxy code to be slightly less hard
  to follow.

- Fix both SPE and TRBE in non-VHE configurations so that they
  do not generate spurious, out of context table walks that
  ultimately lead to very bad HW lockups.

- A small set of patches fixing the Stage-2 MMU freeing in error
  cases.

- Tighten-up accepted SMC immediate value to be only #0 for host
  SMCCC calls.

- The usual cleanups and other selftest churn.
</content>
</entry>
<entry>
<title>irqchip/irq-pic32-evic: Add __maybe_unused for board_bind_eic_interrupt in COMPILE_TEST</title>
<updated>2026-04-07T09:19:02Z</updated>
<author>
<name>Brian Masney</name>
<email>bmasney@redhat.com</email>
</author>
<published>2026-04-03T21:12:17Z</published>
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<id>urn:sha1:1fac04a0a4737c4da3d55d7708931166a4a7136a</id>
<content type='text'>
There are a few ifdefs in this driver so that it can be compiled on all
architectures when COMPILE_TEST is set. board_bind_eic_interrupt is
defined in arch/mips/ for normal usage, however when this driver is
compiled with COMPILE_TEST on other architectures, it is defined as a
static variable inside this driver. This causes the following warning:

    drivers/irqchip/irq-pic32-evic.c:54:15: warning: variable
      'board_bind_eic_interrupt' set but not used [-Wunused-but-set-global]
          54 | static void (*board_bind_eic_interrupt)(int irq,
                                                       int regset);
             |               ^

Annotate the static variable with __maybe_unused to avoid having to put
even more ifdefs into this driver.

Fixes: 282f8b547d51d ("irqchip/irq-pic32-evic: Define board_bind_eic_interrupt for !MIPS builds")
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: Brian Masney &lt;bmasney@redhat.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260403-irq-pic32-evic-unused-v1-1-447cdc0675ec@redhat.com
Closes: https://lore.kernel.org/oe-kbuild-all/202603300715.4HuMMAFb-lkp@intel.com/
</content>
</entry>
<entry>
<title>irqchip/renesas-rzv2h: Kill icu_err string</title>
<updated>2026-04-07T09:19:02Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2026-04-03T08:48:23Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=669d2067e3d095d525c69e675d8b9c738e3616c6'/>
<id>urn:sha1:669d2067e3d095d525c69e675d8b9c738e3616c6</id>
<content type='text'>
Replace the string variable icu_err by its expanded value where needed,
to improve readability.

This reduces generated code size by 16 bytes.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/c7472bec20dea2c4d63e390e8e293b7d7003ef39.1775205874.git.geert+renesas@glider.be
</content>
</entry>
<entry>
<title>irqchip/renesas-rzv2h: Kill swint_names[]</title>
<updated>2026-04-07T09:19:01Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2026-04-03T08:48:22Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=8c7ffedff0db88837de11cfaf3e5367e0b77bc4c'/>
<id>urn:sha1:8c7ffedff0db88837de11cfaf3e5367e0b77bc4c</id>
<content type='text'>
The array swint_names[] just contains expansions of "int-ca55-%u".
Replace it by formatting the strings where needed, to improve
readability.

Despite the two error messages can no longer be shared with the ICU
error cases, this reduces generated code size by 56 bytes.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Reviewed-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt;
Link: https://patch.msgid.link/aceab3fbc307ef428dfd62d8d846b68704dea012.1775205874.git.geert+renesas@glider.be
</content>
</entry>
<entry>
<title>irqchip/renesas-rzv2h: Kill swint_idx[]</title>
<updated>2026-04-07T09:19:01Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2026-04-03T08:48:21Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=fc4c926ccd34d4ee75669991693b47a9b8645a6c'/>
<id>urn:sha1:fc4c926ccd34d4ee75669991693b47a9b8645a6c</id>
<content type='text'>
The array swint_idx[] just contains an identity mapping.
Replace it by using the index directly, to simplify the code.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Reviewed-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt;
Link: https://patch.msgid.link/0f32ba2a4701311710d02ff4fa2fd472b56745c4.1775205874.git.geert+renesas@glider.be
</content>
</entry>
<entry>
<title>irqchip/renesas-rzg2l: Add NMI support</title>
<updated>2026-04-01T16:41:58Z</updated>
<author>
<name>Biju Das</name>
<email>biju.das.jz@bp.renesas.com</email>
</author>
<published>2026-04-01T11:45:00Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=0e5988549dc73d985cc12c4cb438771ced74f522'/>
<id>urn:sha1:0e5988549dc73d985cc12c4cb438771ced74f522</id>
<content type='text'>
The RZ/G2L SoC has an NMI interrupt. Add support for the NMI interrupt.

Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@kernel.org&gt;
Link: https://patch.msgid.link/20260401114504.332825-1-biju.das.jz@bp.renesas.com
</content>
</entry>
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