user/sven/linux.git/drivers/memory/tegra/mc.c, branch next/master

memory: tegra: Add MC error logging support for Tegra264

2026-03-07T17:02:48Z

In Tegra264, different components from memory subsystems like Memory Controller Fabric (MCF), HUB, HUB Common (HUBC), Side Band Shim (SBS) and channels have different interrupt lines for receiving memory controller error interrupts. Add support for logging memory controller errors reported by these memory subsystems on Tegra264 by: - Renaming tegra_mc_error_names array to tegra20_mc_error_names because it has a different bit index for error names compared to Tegra264. - Defining the intmask registers and mask values supported for Tegra264. - Registering interrupt handlers for interrupts associated with these different MC components which read the interrupt status registers to determine the type of violation that occurred. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-7-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Prepare for supporting multiple intmask registers

2026-03-07T17:02:41Z

Add a new structure for the intmask register e.g. MC_INTMASK_0 and it's mask value. Add an array of these new structures to prepare for supporting multiple intmask registers. This is done in preparation for adding support for Tegra264 which supports multiple intmask registers. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski

memory: tegra: Group SoC specific fields

2026-03-07T17:02:29Z

Introduce new SoC specific fields in tegra_mc_soc struct for high address mask and error status type mask because Tegra264 has different values for these than the existing devices. Error status registers e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the error. In order to obtain such type of error from error status register, we use error status type mask. Similarly, these error status registers have bits which indicate the higher address bits of the address responsible for mc error. In order to obtain such higher address, we use high address mask. Make this change to prepare for adding MC interrupt support for Tegra264. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add support for multiple IRQs

2026-03-07T16:59:37Z

Add support to handle multiple MC interrupts lines, as supported by Tegra264. Turn the single IRQ handler callback into a counted array to allow specifying a separate handler for each interrupt. Move IRQ handlers into tegra_mc_soc struct, so as to specify SoC specific values. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-4-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Group error handling related registers

2026-03-07T16:59:35Z

Group MC error related registers into a struct as they could have SoC specific values. Tegra264 has different register offsets than the existing devices and so in order to add support for Tegra264 we need to first make this change. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra-mc: Use %pe format

2026-03-05T11:54:59Z

Make code printing pointer error value a bit simpler and fix coccinelle suggestion: tegra/mc.c:975:4-11: WARNING: Consider using %pe to print PTR_ERR() Signed-off-by: Krzysztof Kozlowski Acked-by: Thierry Reding Link: https://patch.msgid.link/20260226-memory-simplify-v1-4-ccb94f378628@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski

memory: tegra-mc: Simplify printing PTR_ERR with dev_err_probe

2026-03-05T11:54:58Z

Use dev_err_probe() to simplify the code and fix Coccinelle warning: tegra/mc.c:513:52-59: WARNING: Consider using %pe to print PTR_ERR() Signed-off-by: Krzysztof Kozlowski Acked-by: Thierry Reding Link: https://patch.msgid.link/20260226-memory-simplify-v1-3-ccb94f378628@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski

memory: tegra-mc: Drop tegra_mc_setup_latency_allowance() return value

2026-03-05T11:54:58Z

tegra_mc_setup_latency_allowance() only succeeds, thus its return value can be dropped making code a bit simpler. Signed-off-by: Krzysztof Kozlowski Acked-by: Thierry Reding Link: https://patch.msgid.link/20260226-memory-simplify-v1-2-ccb94f378628@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add Tegra264 MC and EMC support

2025-07-11T14:49:42Z

Add support to enable Memory Controller (MC) and External Memory Controller (EMC) drivers for Tegra264. The nodes for MC and EMC are mostly the same as Tegra234 but differ in number of channels and interrupt numbers. The patch also adds the bandwidth manager definitions required for Tegra264 and uses them to populate the memory client table. All of these are needed to properly enable memory interconnect (ICC) support. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250709222147.3758356-3-thierry.reding@gmail.com Signed-off-by: Thierry Reding

memory: tegra-mc: simplify with scoped for each OF child loop

2024-08-21T11:23:34Z

Use scoped for_each_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/20240816-cleanup-h-of-node-put-memory-v2-7-9eed0ee16b78@linaro.org Signed-off-by: Krzysztof Kozlowski