Linux Kernel https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v4.7 2015-12-14T15:11:35Z 2015-12-14T15:11:35Z Vince Hsu vince.h@nvidia.com 2015-09-29T09:58:51Z urn:sha1:e2127ae7a5e80eb53ad431c39145767391da40cd Tegra124 was accidentally left out when the number of TLB lines was parameterized in commit 11cec15bf3fb ("iommu/tegra-smmu: Parameterize number of TLB lines"). Fortunately this doesn't cause any noticeable regressions upstream, presumably because there aren't any use-cases that exercise enough pressure on the SMMU. But it is a regression nonetheless, so let's fix it. Fixes: 11cec15bf3fb ("iommu/tegra-smmu: Parameterize number of TLB lines") Signed-off-by: Vince Hsu <vince.h@nvidia.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> [treding@nvidia.com: extract from unrelated patch] Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-09-09T00:22:35Z Linus Torvalds torvalds@linux-foundation.org 2015-09-09T00:22:35Z urn:sha1:9a9952bbd76a13fc2c95c28f09ba1801a3664929 Pull iommu updates for from Joerg Roedel: "This time the IOMMU updates are mostly cleanups or fixes. No big new features or drivers this time. In particular the changes include: - Bigger cleanup of the Domain<->IOMMU data structures and the code that manages them in the Intel VT-d driver. This makes the code easier to understand and maintain, and also easier to keep the data structures in sync. It is also a preparation step to make use of default domains from the IOMMU core in the Intel VT-d driver. - Fixes for a couple of DMA-API misuses in ARM IOMMU drivers, namely in the ARM and Tegra SMMU drivers. - Fix for a potential buffer overflow in the OMAP iommu driver's debug code - A couple of smaller fixes and cleanups in various drivers - One small new feature: Report domain-id usage in the Intel VT-d driver to easier detect bugs where these are leaked" * tag 'iommu-updates-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (83 commits) iommu/vt-d: Really use upper context table when necessary x86/vt-d: Fix documentation of DRHD iommu/fsl: Really fix init section(s) content iommu/io-pgtable-arm: Unmap and free table when overwriting with block iommu/io-pgtable-arm: Move init-fn declarations to io-pgtable.h iommu/msm: Use BUG_ON instead of if () BUG() iommu/vt-d: Access iomem correctly iommu/vt-d: Make two functions static iommu/vt-d: Use BUG_ON instead of if () BUG() iommu/vt-d: Return false instead of 0 in irq_remapping_cap() iommu/amd: Use BUG_ON instead of if () BUG() iommu/amd: Make a symbol static iommu/amd: Simplify allocation in irq_remapping_alloc() iommu/tegra-smmu: Parameterize number of TLB lines iommu/tegra-smmu: Factor out tegra_smmu_set_pde() iommu/tegra-smmu: Extract tegra_smmu_pte_get_use() iommu/tegra-smmu: Use __GFP_ZERO to allocate zeroed pages iommu/tegra-smmu: Remove PageReserved manipulation iommu/tegra-smmu: Convert to use DMA API iommu/tegra-smmu: smmu_flush_ptc() wants device addresses ... 2015-08-13T15:05:28Z Thierry Reding treding@nvidia.com 2015-08-06T12:20:31Z urn:sha1:11cec15bf3fb498206ef63b1fa26c27689e02d0e The number of TLB lines was increased from 16 on Tegra30 to 32 on Tegra114 and later. Parameterize the value so that the initial default can be set accordingly. On Tegra30, initializing the value to 32 would effectively disable the TLB and hence cause massive latencies for memory accesses translated through the SMMU. This is especially noticeable for isochronuous clients such as display, whose FIFOs would continuously underrun. Fixes: 891846516317 ("memory: Add NVIDIA Tegra memory controller support") Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-08-13T14:07:52Z Thierry Reding treding@nvidia.com 2015-03-23T09:45:12Z urn:sha1:588c43a7bd5a53ae523b318e1db16bdd59963a3c Add the table of memory clients and SWGROUPs for Tegra210 to enable SMMU support for this new SoC. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-08-13T14:07:52Z Paul Walmsley paul@pwsan.com 2015-06-04T19:33:48Z urn:sha1:3c01cf3befa66cc21f06672685cf59a53056887a Recent versions of the Tegra MC hardware extend the size of the client ID bitfield in the MC_ERR_STATUS register by one bit. While one could simply extend the bitfield for older hardware, that would allow data from reserved bits into the driver code, which is generally a bad idea on principle. So this patch instead passes in the client ID mask from from the per-SoC MC data. There's no MC support for T210 (yet), but when that support winds up in the kernel, the appropriate soc->client_id_mask value for that chip will be 0xff. Based on an original patch by David Ung <davidu@nvidia.com>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: David Ung <davidu@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-08-13T14:06:40Z Russell King rmk+kernel@arm.linux.org.uk 2015-07-27T12:29:36Z urn:sha1:4b3c7d10765403ab19628fb7d530b8ce1c50b81d Drivers should not be using __cpuc_* functions nor outer_cache_flush() directly. This change partly cleans up tegra-smmu.c. The only difference between cache handling of the tegra variants is Denver, which omits the call to outer_cache_flush(). This is due to Denver being an ARM64 CPU, and the ARM64 architecture does not provide this function. (This, in itself, is a good reason why these should not be used.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> [treding@nvidia.com: fix build failure on 64-bit ARM] Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-07-16T07:51:47Z Thierry Reding treding@nvidia.com 2015-05-18T15:35:30Z urn:sha1:30a636f984984655ad5350e73a6a3141c9ba85ae In order to ease testing, expose the list of supported EMC frequencies via debugfs. Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-13T15:59:35Z Arnd Bergmann arnd@arndb.de 2015-05-13T15:59:35Z urn:sha1:44fb3026ad28d2a2b935dc9c47ec2dffadca3f35 Merge "ARM: tegra: Add EMC driver for v4.2-rc1" from Thierry Reding: This introduces the EMC driver that's required to scale the external memory frequency. * tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Add EMC frequency debugfs entry memory: tegra: Add EMC (external memory controller) driver memory: tegra: Add API needed by the EMC driver of: Add Tegra124 EMC bindings of: Document timings subnode of nvidia,tegra-mc 2015-05-05T09:39:48Z Mikko Perttunen mperttunen@nvidia.com 2015-03-12T14:48:06Z urn:sha1:9c77a81f215bfeee8f96c50c8ab27dbebffec80d This file in debugfs can be used to get or set the EMC frequency. Reading the file will return the currently set frequency in Hz, while writing the file sets the specified frequency rounded to the next highest frequency supported by the board. Will be very useful when tuning memory scaling. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> [treding@nvidia.com: add "emc" debugfs directory] Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-05T09:12:17Z Mikko Perttunen mperttunen@nvidia.com 2015-03-12T14:48:03Z urn:sha1:73a7f0a90641b09300d47308682b674c570dd6a2 Implements functionality needed to change the rate of the memory bus clock. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>