<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/memory/tegra, branch v5.9.8</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.9.8</id>
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<updated>2020-11-05T10:51:53Z</updated>
<entry>
<title>memory: tegra: Remove GPU from DRM IOMMU group</title>
<updated>2020-11-05T10:51:53Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-09-01T15:32:48Z</published>
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<id>urn:sha1:38ae02bf311295db0e5a4c4fca8d4f0e78044c2e</id>
<content type='text'>
commit ea90f66f2a8629dde07328df0b8314aae5e54a47 upstream.

Commit 63a613fdb16c ("memory: tegra: Add gr2d and gr3d to DRM IOMMU
group") added the GPU to the DRM IOMMU group, which doesn't make any
sense. This causes problems when Nouveau tries to attach to the SMMU
and causes it to fall back to using the DMA API.

Remove the GPU from the DRM groups to restore the old behaviour. The
GPU should always have its own IOMMU domain to make sure it can map
buffers into contiguous chunks (for big page support) without getting
in the way of mappings from the DRM group.

Cc: &lt;stable@vger.kernel.org&gt;
Fixes: 63a613fdb16c ("memory: tegra: Add gr2d and gr3d to DRM IOMMU group")
Reported-by: Matias Zuniga &lt;matias.nicolas.zc@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20200901153248.1831263-1-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>memory: tegra: Add Tegra132 compatible string match</title>
<updated>2020-07-15T09:55:21Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-06-12T08:59:00Z</published>
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<id>urn:sha1:46c019239fb263922d2881847dd6b614c814d867</id>
<content type='text'>
Ensure that the driver will bind against the Tegra132 instantiation of
the external memory controller. While the two are roughly the same from
a capability perspective, they do require some incompatible changes to
the programming sequences and therefore need separate compatible
strings.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Fix KCONFIG variables for Tegra186 and Tegra194</title>
<updated>2020-07-14T15:37:05Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2020-07-12T10:33:47Z</published>
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<id>urn:sha1:0454efbcb2611d338b8d744b9cafeb017cb966bf</id>
<content type='text'>
Commit a127e690b051 ("memory: tegra: Add support for the Tegra194 memory
controller") and commit 4e04b88633ae ("memory: tegra: Only include
support for enabled SoCs") incorrectly added the KCONFIG variables
CONFIG_ARCH_TEGRA186_SOC and CONFIG_ARCH_TEGRA194_SOC to the Tegra EMC
driver. These KCONFIG variables do not exist and prevent the EMC driver
from being probed on Tegra186 and Tegra194. These KCONFIG variable
names are simply missing one underscore and so fix this by adding the
necessary underscore to the variable names.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Delete some dead code</title>
<updated>2020-06-22T11:54:58Z</updated>
<author>
<name>Dan Carpenter</name>
<email>dan.carpenter@oracle.com</email>
</author>
<published>2020-05-08T11:42:46Z</published>
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<id>urn:sha1:5a6b5d53833c92f05d9892e96d9034ff05df551d</id>
<content type='text'>
The debugfs_create_dir() function never returns NULL and anyway the
correct behavior is to ignore errors in this situation.  The
debugfs_create_file() will become a no-op if "emc-&gt;debugfs.root" is an
error pointer.

Signed-off-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Avoid unused function warnings</title>
<updated>2020-06-22T11:54:58Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2020-04-08T19:00:30Z</published>
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<id>urn:sha1:2de758997e69a5f971716c90a9cdc410133283d7</id>
<content type='text'>
The suspend/resume functions have no callers depending on
configuration, so they must be marked __maybe_unused to
avoid these harmless warnings:

drivers/memory/tegra/tegra186.c:1578:12: error: 'tegra186_mc_resume' defined but not used [-Werror=unused-function]
 1578 | static int tegra186_mc_resume(struct device *dev)
      |            ^~~~~~~~~~~~~~~~~~
drivers/memory/tegra/tegra186.c:1573:12: error: 'tegra186_mc_suspend' defined but not used [-Werror=unused-function]
 1573 | static int tegra186_mc_suspend(struct device *dev)
      |            ^~~~~~~~~~~~~~~~~~~

Fixes: 177602b00641 ("memory: tegra: Add system sleep support")
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Drop &lt;linux/clk-provider.h&gt;</title>
<updated>2020-06-22T11:54:58Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2020-05-06T12:32:36Z</published>
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<id>urn:sha1:1b93fadf2a7e40d221513247019925425384d8d1</id>
<content type='text'>
The Tegra EMC scaling support code is not a clock provider, but merely a
clock consumer, and thus does not need to include
&lt;linux/clk-provider.h&gt;.

Fixes: 0bf368c5b2cf ("memory: tegra: Add EMC scaling support code for Tegra210")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Fix an error handling path in tegra186_emc_probe()</title>
<updated>2020-06-22T11:54:58Z</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2020-05-06T20:09:07Z</published>
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<id>urn:sha1:c3d4eb3bf6ad32466555b31094f33a299444f795</id>
<content type='text'>
The call to tegra_bpmp_get() must be balanced by a call to
tegra_bpmp_put() in case of error, as already done in the remove
function.

Add an error handling path and corresponding goto.

Fixes: 52d15dd23f0b ("memory: tegra: Support DVFS on Tegra186 and later")
Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra30-emc: Poll EMC-CaR handshake instead of waiting for interrupt</title>
<updated>2020-06-22T11:54:57Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-03-19T19:36:48Z</published>
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<id>urn:sha1:930c68180ffb059647d75ee28918bcb87f18d788</id>
<content type='text'>
The memory clock-rate change could be running on a non-boot CPU, while the
boot CPU handles the EMC interrupt. This introduces an unnecessary latency
since boot CPU should handle the interrupt and then notify the sibling CPU
about clock-rate change completion. In some rare cases boot CPU could be
in uninterruptible state for a significant time (like in a case of KASAN +
NFS root), it could get to the point that completion timeouts before boot
CPU gets a chance to handle interrupt. The solution is to get rid of the
completion and replace it with interrupt-status polling.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra20-emc: Poll EMC-CaR handshake instead of waiting for interrupt</title>
<updated>2020-06-22T11:54:57Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-03-19T19:36:47Z</published>
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<id>urn:sha1:adbcec8862cd7e3737e1488a98239f95dc45688f</id>
<content type='text'>
The memory clock-rate change could be running on a non-boot CPU, while the
boot CPU handles the EMC interrupt. This introduces an unnecessary latency
since boot CPU should handle the interrupt and then notify the sibling CPU
about clock-rate change completion. In some rare cases boot CPU could be
in uninterruptible state for a significant time (like in a case of KASAN +
NFS root), it could get to the point that completion timeouts before boot
CPU gets a chance to handle interrupt. The solution is to get rid of the
completion and replace it with interrupt-status polling.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Support derated timings on Tegra210</title>
<updated>2020-06-22T11:54:57Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-04-03T18:03:15Z</published>
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<id>urn:sha1:0553d7b204ef48091e76753175d21d0c30b7ae2a</id>
<content type='text'>
Derated timings are used to ensure that the memory chips keep operating
correctly at high temperatures. This adds code to support polling of the
chip operating state when high temperatures are measured on the chip and
change the refresh mode accordingly. Under very high temperatures, the
driver will switch to the derated tables to ensure proper operation of
the memory chips.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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