user/sven/linux.git/drivers/mtd/nand/raw, branch master

Merge tag 'mtd/for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

2026-04-18T00:57:04Z

Pull MTD updates from Miquel Raynal: "MTD changes: - mtdconcat finally makes it in, after several years of being merged and reverted - Baikal SoC support is being removed, so MTD bits are being removed as well - misc cleanups NAND changes: - SunXi driver support for new versions of the Allwinner NAND controller. - DT-binding improvements and cleanups. - A few fixes (Realtek ECC and Winbond SPI NAND), aside with the usual load of misc changes. SPI NOR fixes: - Enable die erase on MT35XU02GCBA. We knew this flash needed this fixup since 7f77c561e227 ("mtd: spi-nor: micron-st: add TODO for fixing mt35xu02gcba") but did not add it due to lack of hardware to test on. - Fix locking on some Winbond w25q series flashes. - Fix Auto Address Increment (AAI) writes on SST that flashes that start on odd address. The write enable latch needs to be set again after the single byte program" * tag 'mtd/for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (44 commits) mtd: spinand: winbond: Declare the QE bit on W25NxxJW mtd: spi-nor: micron-st: Enable die erase support for MT35XU02GCBA mtd: spi-nor: winbond: Fix locking support for w25q256jw mtd: spi-nor: sst: Fix write enable before AAI sequence mtd: spi-nor: winbond: Fix locking support for w25q64jvm mtd: spi-nor: winbond: Fix locking support for w25q256jwm dt-bindings: mtd: mxc-nand: add missing compatible string and ref to nand-controller-legacy.yaml dt-bindings: mtd: gpmi-nand: ref to nand-controller-legacy.yaml dt-bindings: mtd: refactor NAND bindings and add nand-controller-legacy.yaml mtd: spinand: winbond: Clarify when to enable the HS bit mtd: rawnand: sunxi: introduce maximize variable user data length mtd: rawnand: sunxi: fix typos in comments mtd: rawnand: sunxi: change error prone variable name mtd: rawnand: sunxi: remove dead code mtd: rawnand: sunxi: make the code more self-explanatory mtd: rawnand: sunxi: replace hard coded value by a define - take2 mtd: rawnand: sunxi: do not count BBM bytes twice mtd: rawnand: sunxi: fix sunxi_nfc_hw_ecc_read_extra_oob mtd: rawnand: sunxi: sunxi_nand_ooblayout_free code clarification mtd: cmdlinepart: use a flexible array member ...

MIPS/mtd: Handle READY GPIO in generic NAND platform data

2026-04-13T13:41:56Z

The callbacks into the MIPS RB532 platform to read the GPIO pin indicating that the NAND chip is ready are oldschool and does not assign GPIOs as properties to the NAND device. Add a capability to the generic platform NAND chip driver to use a GPIO line to detect if a NAND chip is ready and override the platform-local drv_ready() callback with this check if the GPIO is present. This makes it possible to drop the legacy include header from the RB532 devices. Signed-off-by: Linus Walleij Acked-by: Miquel Raynal Signed-off-by: Thomas Bogendoerfer

mtd: rawnand: sunxi: introduce maximize variable user data length

2026-03-25T14:27:30Z

In Allwinner SoCs, user data can be added in OOB before each ECC data. For older SoCs like A10, the user data size was the size of a register (4 bytes) and was mandatory before each ECC step. So, the A10 OOB Layout is: [4Bytes USER_DATA_STEP0] [ECC_STEP0 bytes] [4bytes USER_DATA_STEP1] [ECC_STEP1 bytes] ... NB: the BBM is stored at the beginning of the USER_DATA_STEP0. Now, for H6/H616 NAND flash controller, this user data can have a different size for each step. So, we are maximizing the user data length to use as many OOB bytes as possible. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand controller") Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: fix typos in comments

2026-03-25T14:27:30Z

Fix lenghts -> lengths and chuncks -> chunks Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: change error prone variable name

2026-03-25T14:27:30Z

In sunxi_nand_hw_ecc_ctrl_init(), i is used as a loop index variable and at the same time as the value used to set ECC mode in ECC control register. To prevent it from being re-used as a loop variable, let's change the naming to ecc_mode. No functional change. Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: remove dead code

2026-03-25T14:27:30Z

sunxi_nand_ooblayout_free() is only used in a code path where engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST So the other cases can be removed. Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: make the code more self-explanatory

2026-03-25T14:27:30Z

In sunxi_nfc_hw_ecc_{read,write}_chunk(), the ECC step was forced to 0, the reason is not trivial to get when reading the code. The explanation is that, from the NAND flash controller perspective, we are indeed at step 0 for user data length and ECC errors. Just add a const value with an explanation to clarify things. Acked-by: Jernej Skrabec Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: replace hard coded value by a define - take2

2026-03-25T14:27:30Z

The user data length (4) has been replaced almost all over the file, but 2 places were forgotten. The user data is placed before the ECC, for each step. So, in sunxi_nfc_hw_ecc_read_extra_oob(), the offset of the user data in OOB is indeed ((ecc->bytes + USER_DATA_SZ) * ecc->steps); And in sunxi_nand_ooblayout_ecc(), the offset of the ECC chunk in OOB is the same offset plus the current user data size: section * (ecc->bytes + USER_DATA_SZ) + USER_DATA_SZ; Reviewed-by: Jernej Skrabec Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: do not count BBM bytes twice

2026-03-25T14:27:30Z

BBM is already part of USER_DATA section, so we should not remove it twice This was working ok because we are on the safe size, advertising that there was 2 bytes less available than in reality. But we can't change old platforms, since it may lead to a different ECC strength, so, introduce a legacy flag for old platforms, and switch the new platforms to the correct count. Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal

mtd: rawnand: sunxi: fix sunxi_nfc_hw_ecc_read_extra_oob

2026-03-25T14:27:30Z

When dumping the OOB, the bytes at the end where actually copied from the beginning of the OOB instead of current_offset. That leads to something like: OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b instead of: OOB: ff ff ff ff ff ff ff ff ea 19 00 3a 83 db aa 8d OOB: 99 09 c8 9a 90 36 35 7d aa 15 13 07 3d 97 b2 a4 OOB: a8 bb 19 b3 07 e9 f6 25 52 d7 1a 23 e2 7e 0a e4 OOB: 52 8a 09 d2 1a 86 3d cf b4 99 43 13 d3 90 33 0b OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff (example with BCH16, user data [8,0], no scrambling) *cur_off (offset from the beginning of the page) was compared to offset (offset from the beginning of the OOB), and then, the nand_change_read_column_op() sets the current position to the beginning of the OOB instead of OOB+offset Fixes: 15d6f118285f ("mtd: rawnand: sunxi: Stop supporting ECC_HW_SYNDROME mode") Reviewed-by: Jernej Skrabec Signed-off-by: Richard Genoud Signed-off-by: Miquel Raynal