user/sven/linux.git/drivers/net/fddi, branch v4.4.283

FDDI: defxx: Make MMIO the configuration default except for EISA

2021-05-22T08:38:29Z

commit 193ced4a79599352d63cb8c9e2f0c6043106eb6a upstream. Recent versions of the PCI Express specification have deprecated support for I/O transactions and actually some PCIe host bridges, such as Power Systems Host Bridge 4 (PHB4), do not implement them. The default kernel configuration choice for the defxx driver is the use of I/O ports rather than MMIO for PCI and EISA systems. It may have made sense as a conservative backwards compatible choice back when MMIO operation support was added to the driver as a part of TURBOchannel bus support. However nowadays this configuration choice makes the driver unusable with systems that do not implement I/O transactions for PCIe. Make DEFXX_MMIO the configuration default then, except where configured for EISA. This exception is because an EISA adapter can have its MMIO decoding disabled with ECU (EISA Configuration Utility) and therefore not available with the resource allocation infrastructure we implement, while port I/O is always readily available as it uses slot-specific addressing, directly mapped to the slot an option card has been placed in and handled with our EISA bus support core. Conversely a kernel that supports modern systems which may not have I/O transactions implemented for PCIe will usually not be expected to handle legacy EISA systems. The change of the default will make it easier for people, including but not limited to distribution packagers, to make a working choice for the driver. Update the option description accordingly and while at it replace the potentially ambiguous PIO acronym with IOP for "port I/O" vs "I/O ports" according to our nomenclature used elsewhere. Signed-off-by: Maciej W. Rozycki Fixes: e89a2cfb7d7b ("[TC] defxx: TURBOchannel support") Cc: stable@vger.kernel.org # v2.6.21+ Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman

FDDI: defxx: Bail out gracefully with unassigned PCI resource for CSR

2021-05-22T08:38:20Z

commit f626ca682912fab55dff15469ce893ae16b65c7e upstream. Recent versions of the PCI Express specification have deprecated support for I/O transactions and actually some PCIe host bridges, such as Power Systems Host Bridge 4 (PHB4), do not implement them. For those systems the PCI BARs that request a mapping in the I/O space have the length recorded in the corresponding PCI resource set to zero, which makes it unassigned: # lspci -s 0031:02:04.0 -v 0031:02:04.0 FDDI network controller: Digital Equipment Corporation PCI-to-PDQ Interface Chip [PFI] FDDI (DEFPA) (rev 02) Subsystem: Digital Equipment Corporation FDDIcontroller/PCI (DEFPA) Flags: bus master, medium devsel, latency 136, IRQ 57, NUMA node 8 Memory at 620c080020000 (32-bit, non-prefetchable) [size=128] I/O ports at [disabled] Memory at 620c080030000 (32-bit, non-prefetchable) [size=64K] Capabilities: [50] Power Management version 2 Kernel driver in use: defxx Kernel modules: defxx # Regardless the driver goes ahead and requests it (here observed with a Raptor Talos II POWER9 system), resulting in an odd /proc/ioport entry: # cat /proc/ioports 00000000-ffffffffffffffff : 0031:02:04.0 # Furthermore, the system gets confused as the driver actually continues and pokes at those locations, causing a flood of messages being output to the system console by the underlying system firmware, like: defxx: v1.11 2014/07/01 Lawrence V. Stefani and others defxx 0031:02:04.0: enabling device (0140 -> 0142) LPC[000]: Got SYNC no-response error. Error address reg: 0xd0010000 IPMI: dropping non severe PEL event LPC[000]: Got SYNC no-response error. Error address reg: 0xd0010014 IPMI: dropping non severe PEL event LPC[000]: Got SYNC no-response error. Error address reg: 0xd0010014 IPMI: dropping non severe PEL event and so on and so on (possibly intermixed actually, as there's no locking between the kernel and the firmware in console port access with this particular system, but cleaned up above for clarity), and once some 10k of such pairs of the latter two messages have been produced an interace eventually shows up in a useless state: 0031:02:04.0: DEFPA at I/O addr = 0x0, IRQ = 57, Hardware addr = 00-00-00-00-00-00 This was not expected to happen as resource handling was added to the driver a while ago, because it was not known at that time that a PCI system would be possible that cannot assign port I/O resources, and oddly enough `request_region' does not fail, which would have caught it. Correct the problem then by checking for the length of zero for the CSR resource and bail out gracefully refusing to register an interface if that turns out to be the case, producing messages like: defxx: v1.11 2014/07/01 Lawrence V. Stefani and others 0031:02:04.0: Cannot use I/O, no address set, aborting 0031:02:04.0: Recompile driver with "CONFIG_DEFXX_MMIO=y" Keep the original check for the EISA MMIO resource as implemented, because in that case the length is hardwired to 0x400 as a consequence of how the compare/mask address decoding works in the ESIC chip and it is only the base address that is set to zero if MMIO has been disabled for the adapter in EISA configuration, which in turn could be a valid bus address in a legacy-free system implementing PCI, especially for port I/O. Where the EISA MMIO resource has been disabled for the adapter in EISA configuration this arrangement keeps producing messages like: eisa 00:05: EISA: slot 5: DEC3002 detected defxx: v1.11 2014/07/01 Lawrence V. Stefani and others 00:05: Cannot use MMIO, no address set, aborting 00:05: Recompile driver with "CONFIG_DEFXX_MMIO=n" 00:05: Or run ECU and set adapter's MMIO location with the last two lines now swapped for easier handling in the driver. There is no need to check for and catch the case of a port I/O resource not having been assigned for EISA as the adapter uses the slot-specific I/O space, which gets assigned by how EISA has been specified and maps directly to the particular slot an option card has been placed in. And the EISA variant of the adapter has additional registers that are only accessible via the port I/O space anyway. While at it factor out the error message calls into helpers and fix an argument order bug with the `pr_err' call now in `dfx_register_res_err'. Signed-off-by: Maciej W. Rozycki Fixes: 4d0438e56a8f ("defxx: Clean up DEFEA resource management") Cc: stable@vger.kernel.org # v3.19+ Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman

net/fddi: remove HWM_REVERSE() macro

2015-08-14T04:12:17Z

HWM_REVERSE() macro is unused, remove it. Signed-off-by: yalin wang Signed-off-by: David S. Miller

fddi: print an address with %p format specifier rather than %x

2015-06-07T07:31:22Z

The debug is printing the struct smt_header * address using the %x format specifier. Fix it to use %p instead. Signed-off-by: Colin Ian King Signed-off-by: David S. Miller

net: fddi: skfp: smt.c: Remove unused function

2015-01-02T21:36:07Z

Remove the function smt_ifconfig() that is not used anywhere. This was partially found by using a static code analysis program called cppcheck. Signed-off-by: Rickard Strandqvist Signed-off-by: David S. Miller

defxx: Clean up DEFEA resource management

2014-11-21T21:37:13Z

Reserve DEFEA resources according to actual use. There are three regions, for the ESIC ASIC's CSRs, for the discrete Burst Holdoff register, and for the PDQ ASIC's CSRs. The latter is mapped in the memory or port I/O address space depending on configuration. The two formers are hardwired and always mapped in the port I/O address space. Signed-off-by: Maciej W. Rozycki Signed-off-by: David S. Miller

defxx: Disable DEFEA's ESIC I/O decoding on shutdown

2014-11-21T21:37:13Z

Make sure the option card does not respond after shutdown by disabling it via ESIC's Expansion Board Control register. Also disable memory and port I/O decoders, the latter in particular to disable slot-specific I/O decoding that otherwise remains active even in the board is disabled. Signed-off-by: Maciej W. Rozycki Signed-off-by: David S. Miller

defxx: Correct DEFEA's ESIC MMIO decoding

2014-11-21T21:37:13Z

Use ESIC's memory area 1 (MEMCS1) and its Memory Address High Compare and Memory Address Low Compare registers to set up the MMIO range for decoding accesses to PDQ ASIC registers. Previously the PDQ ASIC was thought to be addressable with the memory area 0 (MEMCS0) and its Memory Address Compare and Memory Address Mask registers. The MMIO range allocated for the option card is preset via ECU (EISA Configuration Utility) and can be disabled, so handle such a case gracefully too. Signed-off-by: Maciej W. Rozycki Signed-off-by: David S. Miller

defxx: Fix DEFPA enable error propagation

2014-11-21T21:37:13Z

Correctly propagate the error code from `pci_enable_device' if non zero. Currently a failure of this function is correctly recognized and device initialization abandoned, however a successful completion code returned. Signed-off-by: Maciej W. Rozycki Signed-off-by: David S. Miller

defxx: DEFEA's ESIC port I/O decoding cleanup

2014-09-28T21:22:10Z

Use the slot-specific I/O range for decoding accesses to PDQ ASIC registers (IOCS0) and the discrete Burst Holdoff register (IOCS1) as per the "HD64981F EISA Slave Interface Controller (ESIC)" datasheet. Use disjoint decode ranges now that the assignment of chip selects is known. Update the span of the port I/O resource requested accordingly. Signed-off-by: Maciej W. Rozycki Signed-off-by: David S. Miller