user/sven/linux.git/drivers/net/phy/icplus.c, branch v3.18.48

net: phy: icplus: fix checkpath error

2013-12-18T05:49:02Z

Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: icplus: fix broken INTR pin settings

2013-01-28T05:08:22Z

This patch fixes the setting of the INTR pin that is valid for IP101 A/G device and not for the IP1001. Reported-by: Anunay Saxena Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

net: phy: icplus: Use the RGMII interface mode to configure clock delays

2013-01-28T05:08:22Z

Like several other PHY devices which support RGMII, the IC+1001 allows additional delays to by added to the RX_CLK and TX_CLK signals to compensate for skew between the clock and data signals. Previously this was always enabled, but this change makes use of the different RGMII interface modes to allow the user to specify whether this should be enabled. Signed-off-by: Stuart Menefy Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

phylib: Support registering a bunch of drivers

2012-07-09T07:10:56Z

If registering of one of them fails, all already registered drivers of this module will be unregistered. Use the new register/unregister functions in all drivers registering more than one driver. amd.c, realtek.c: Simplify: directly return registration result. Tested with broadcom.c All others compile-tested. Signed-off-by: Christian Hohnstaedt Signed-off-by: David S. Miller

net: icplus: fix interrupt mask

2012-06-04T16:02:40Z

This patch fixes the interrupt mask for IC101 A/G devices and now enables the link/speed/duplex interrupts. This is done by setting the "INTR pin used" bit and cleaning all the other bits in the Register 17. Reported-by: Stuart Menefy Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

icplus: fix interrupt for IC+ 101A/G and 1001LF

2012-04-19T19:34:18Z

This patch fixes and adds the irq handler for the IC+ 101A/G where we need to read the reg17 to clean the irq. Also remove the flag for the 1001LF where no interrupt can be used for this device. Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

phy:icplus:fix Auto Power Saving in ip101a_config_init.

2012-04-03T22:48:58Z

This patch fixes Auto Power Saving configuration in ip101a_config_init which was broken as there is no phy register write followed after setting IP101A_APS_ON flag. This patch also fixes the return value of ip101a_config_init. Without this patch ip101a_config_init returns 2 which is not an error accroding to IS_ERR and the mac driver will continue accessing 2 as valid pointer to phy_dev resulting in memory fault. Signed-off-by: Srinivas Kandagatla Signed-off-by: David S. Miller

phy: IC+101G and PHY_HAS_INTERRUPT flag

2012-02-23T22:14:26Z

This patch adds the PHY_HAS_INTERRUPT flag for IC+101 device series. Also the patch does a simple dity-up to signal that the driver actually is for IP101A LF and IP101G devices. In fact, these are two similar PHYs that have the same IDs and mainly differ for the EEE capability supported in the G series. Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

netdev/phy/icplus: Correct broken phy_init code

2012-02-23T22:14:26Z

The code for ip1001_config_init() was totally broken if you were not using RGMII. Instead of returning an error code or zero it actually returned the value in the IP1001_SPEC_CTRL_STATUS_2 register. It was also trying to set the IP1001_APS_ON bit , but never actually wrote back the register. The error checking was also incorrect in both this function and the reset function, so this patch fixes that up in a consistent fashion. Signed-off-by: David McKay Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller

net/phy: extra delay only for RGMII interfaces for IC+ IP 1001

2011-10-19T03:50:02Z

The extra delay of 2ns to adjust RX clock phase is actually needed in RGMII mode. Tested on the HDK7108 (STx7108c2). Signed-off-by: Giuseppe Cavallaro Signed-off-by: David S. Miller