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<title>user/sven/linux.git/drivers/pci/hotplug, branch v6.2.7</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2023-03-11T12:50:46Z</updated>
<entry>
<title>PCI: pciehp: Add Qualcomm quirk for Command Completed erratum</title>
<updated>2023-03-11T12:50:46Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2023-02-13T14:49:22Z</published>
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<id>urn:sha1:aa2295bf75714085d58c6c907cdf9d19e2892611</id>
<content type='text'>
[ Upstream commit 82b34b0800af8c9fc9988c290cdc813e0ca0df31 ]

The Qualcomm PCI bridge device (Device ID 0x010e) found in chipsets such as
SC8280XP used in Lenovo Thinkpad X13s, does not set the Command Completed
bit unless writes to the Slot Command register change "Control" bits.

This results in timeouts like below during boot and resume from suspend:

  pcieport 0002:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago)
  ...
  pcieport 0002:00:00.0: pciehp: Timeout on hotplug command 0x13f1 (issued 107724 msec ago)

Add the device to the Command Completed quirk to mark commands "completed"
immediately unless they change the "Control" bits.

Link: https://lore.kernel.org/r/20230213144922.89982-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>PCI: pciehp: Enable Command Completed Interrupt only if supported</title>
<updated>2022-12-07T14:27:20Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2022-09-27T14:19:17Z</published>
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<id>urn:sha1:6d4671b534f6c084e92ef167a52dc47e55f636c4</id>
<content type='text'>
The No Command Completed Support bit in the Slot Capabilities register
indicates whether Command Completed Interrupt Enable is unsupported.

We already check whether No Command Completed Support bit is set in
pcie_wait_cmd(), and do not wait in this case.

Don't enable this Command Completed Interrupt at all if NCCS is set, so
that when users dump configuration space from userspace, the dump does not
confuse them by saying that Command Completed Interrupt is not supported,
but it is enabled.

Link: https://lore.kernel.org/r/20220927141926.8895-2-kabel@kernel.org
Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Signed-off-by: Marek Behún &lt;kabel@kernel.org&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Lukas Wunner &lt;lukas@wunner.de&gt;
</content>
</entry>
<entry>
<title>PCI: shpchp: Remove unused get_mode1_ECC_cap callback</title>
<updated>2022-11-22T20:09:51Z</updated>
<author>
<name>Ian Cowan</name>
<email>ian@linux.cowan.aero</email>
</author>
<published>2022-11-12T14:28:57Z</published>
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<id>urn:sha1:9676f40618df9f8e1ab681486021d6c0df86c5fa</id>
<content type='text'>
The -&gt;get_mode1_ECC_cap callback in the shpchp_hpc_ops struct is never
called, so remove it.

[bhelgaas: squash]
Link: https://lore.kernel.org/r/20221112142859.319733-2-ian@linux.cowan.aero
Link: https://lore.kernel.org/r/20221112142859.319733-3-ian@linux.cowan.aero
Link: https://lore.kernel.org/r/20221112142859.319733-4-ian@linux.cowan.aero
Signed-off-by: Ian Cowan &lt;ian@linux.cowan.aero&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
<entry>
<title>PCI: acpiphp: Avoid setting is_hotplug_bridge for PCIe Upstream Ports</title>
<updated>2022-11-22T19:27:28Z</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2022-11-21T18:16:57Z</published>
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<id>urn:sha1:c63a3be76df678b173c59f1d5dc19a21b2d1c753</id>
<content type='text'>
It is reported that on some systems pciehp binds to an Upstream Port and
attempts to operate it which causes devices below the Port to disappear
from the bus.

This happens because acpiphp sets dev-&gt;is_hotplug_bridge for that Port
(after receiving a Device Check notification on it from the platform
firmware via ACPI) during the enumeration of PCI devices.

get_port_device_capability() sees that dev-&gt;is_hotplug_bridge is set and
adds PCIE_PORT_SERVICE_HP to Port services, which allows pciehp to bind to
the Port in question.

Even though this particular problem can be addressed by making the
portdrv_core checks more robust, it also causes power management to work
differently on the affected systems which generally is not desirable (PCIe
Ports with dev-&gt;is_hotplug_bridge set have to pass additional tests to be
allowed to go into the D3hot/cold power states which affects runtime PM of
devices below these Ports).

For this reason, amend check_hotplug_bridge() with a PCIe type check to
prevent it from setting dev-&gt;is_hotplug_bridge for Upstream Ports.

Suggested-by: Lukas Wunner &lt;lukas@wunner.de&gt;
Link: https://lore.kernel.org/r/2262230.ElGaqSPkdT@kreacher
Reported-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Tested-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Lukas Wunner &lt;lukas@wunner.de&gt;
</content>
</entry>
<entry>
<title>PCI: pciehp: Enable by default if USB4 enabled</title>
<updated>2022-11-15T15:25:21Z</updated>
<author>
<name>Albert Zhou</name>
<email>albert.zhou.50@gmail.com</email>
</author>
<published>2022-11-15T11:38:56Z</published>
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<id>urn:sha1:e67ad9354a9b7621341adec4ac2c63d5269f835d</id>
<content type='text'>
Thunderbolt/USB4 PCIe tunneling depends on native PCIe hotplug.  Enable
pciehp by default if USB4 is enabled.

[bhelgaas: squash, update subject, commit logs, tidy whitespace]
Link: https://lore.kernel.org/r/20221115113857.35800-2-albert.zhou.50@gmail.com
Link: https://lore.kernel.org/r/20221115113857.35800-3-albert.zhou.50@gmail.com
Signed-off-by: Albert Zhou &lt;albert.zhou.50@gmail.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>PCI: hotplug: Clean up include files</title>
<updated>2022-04-05T16:13:33Z</updated>
<author>
<name>Christophe Leroy</name>
<email>christophe.leroy@csgroup.eu</email>
</author>
<published>2022-04-02T10:11:56Z</published>
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<id>urn:sha1:b2851926c6d9d977ff60f613aff95f4900b9620e</id>
<content type='text'>
arch/powerpc/include/asm/prom.h includes some headers that it doesn't need
itself.  Add the missing headers to files that include prom.h so we can
remove them from prom.h.

Link: https://lore.kernel.org/r/79201f5fae8d003164ac36ed3be7789db1bc5ab4.1648833421.git.christophe.leroy@csgroup.eu
Signed-off-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pci-v5.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci</title>
<updated>2022-03-25T20:02:05Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-03-25T20:02:05Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=148a650476955705482dd57e7ffcf105d8b65440'/>
<id>urn:sha1:148a650476955705482dd57e7ffcf105d8b65440</id>
<content type='text'>
Pull pci updates from Bjorn Helgaas:
 "Enumeration:
   - Move the VGA arbiter from drivers/gpu to drivers/pci because it's
     PCI-specific, not GPU-specific (Bjorn Helgaas)
   - Select the default VGA device consistently whether it's enumerated
     before or after VGA arbiter init, which fixes arches that enumerate
     PCI devices late (Huacai Chen)

  Resource management:
   - Support BAR sizes up to 8TB (Dongdong Liu)

  PCIe native device hotplug:
   - Fix "Command Completed" tracking to avoid spurious timouts when
     powering off empty slots (Liguang Zhang)
   - Quirk Qualcomm devices that don't implement Command Completed
     correctly, again to avoid spurious timeouts (Manivannan Sadhasivam)

  Peer-to-peer DMA:
   - Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist
     (Michael J. Ruhl)

  APM X-Gene PCIe controller driver:
   - Revert generic DT parsing changes that broke some machines in the
     field (Marc Zyngier)

  Freescale i.MX6 PCIe controller driver:
   - Allow controller probe to succeed even when no devices currently
     present to allow hot-add later (Fabio Estevam)
   - Enable power management on i.MX6QP (Richard Zhu)
   - Assert CLKREQ# on i.MX8MM so enumeration doesn't hang when no
     device is connected (Richard Zhu)

  Marvell Aardvark PCIe controller driver:
   - Fix MSI and MSI-X support (Marek Behún, Pali Rohár)
   - Add support for ERR and PME interrupts (Pali Rohár)

  Marvell MVEBU PCIe controller driver:
   - Add DT binding and support for "num-lanes" (Pali Rohár)
   - Add support for INTx interrupts (Pali Rohár)

  Microsoft Hyper-V host bridge driver:
   - Avoid unnecessary hypercalls when unmasking IRQs on ARM64 (Boqun
     Feng)

  Qualcomm PCIe controller driver:
   - Add SM8450 DT binding and driver support (Dmitry Baryshkov)

  Renesas R-Car PCIe controller driver:
   - Help the controller get to the L1 state since the hardware can't do
     it on its own (Marek Vasut)
   - Return PCI_ERROR_RESPONSE (~0) for reads that fail on PCIe (Marek
     Vasut)

  SiFive FU740 PCIe controller driver:
   - Drop redundant '-gpios' from DT GPIO lookup (Ben Dooks)
   - Force 2.5GT/s for initial device probe (Ben Dooks)

  Socionext UniPhier Pro5 controller driver:
   - Add NX1 DT binding and driver support (Kunihiko Hayashi)

  Synopsys DesignWare PCIe controller driver:
   - Restore MSI configuration so MSI works after resume (Jisheng
     Zhang)"

* tag 'pci-v5.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (94 commits)
  x86/PCI: Add #includes to asm/pci_x86.h
  PCI: ibmphp: Remove unused assignments
  PCI: cpqphp: Remove unused assignments
  PCI: fu740: Remove unused assignments
  PCI: kirin: Remove unused assignments
  PCI: Remove unused assignments
  PCI: Declare pci_filp_private only when HAVE_PCI_MMAP
  PCI: Avoid broken MSI on SB600 USB devices
  PCI: fu740: Force 2.5GT/s for initial device probe
  PCI: xgene: Revert "PCI: xgene: Fix IB window setup"
  PCI: xgene: Revert "PCI: xgene: Use inbound resources for setup"
  PCI: imx6: Assert i.MX8MM CLKREQ# even if no device present
  PCI: imx6: Invoke the PHY exit function after PHY power off
  PCI: rcar: Use PCI_SET_ERROR_RESPONSE after read which triggered an exception
  PCI: rcar: Finish transition to L1 state in rcar_pcie_config_access()
  PCI: dwc: Restore MSI Receiver mask during resume
  PCI: fu740: Drop redundant '-gpios' from DT GPIO lookup
  PCI/VGA: Replace full MIT license text with SPDX identifier
  PCI/VGA: Use unsigned format string to print lock counts
  PCI/VGA: Log bridge control messages when adding devices
  ...
</content>
</entry>
<entry>
<title>Merge branch 'pci/misc'</title>
<updated>2022-03-22T22:16:21Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2022-03-22T22:16:21Z</published>
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<id>urn:sha1:73c82469bd88ce1c9a4403f34582e544e77f4854</id>
<content type='text'>
- Update the aer-inject URL (Yicong Yang)

- Declare pci_filp_private only when HAVE_PCI_MMAP to avoid unused struct
  definition (Krzysztof Wilczyński)

- Remove unused assignments (Bjorn Helgaas)

- Add #includes to asm/pci_x86.h to prevent build errors (Randy Dunlap)

* pci/misc:
  x86/PCI: Add #includes to asm/pci_x86.h
  PCI: ibmphp: Remove unused assignments
  PCI: cpqphp: Remove unused assignments
  PCI: fu740: Remove unused assignments
  PCI: kirin: Remove unused assignments
  PCI: Remove unused assignments
  PCI: Declare pci_filp_private only when HAVE_PCI_MMAP
  PCI/AER: Update aer-inject URL
</content>
</entry>
<entry>
<title>Merge branch 'pci/hotplug'</title>
<updated>2022-03-22T22:16:20Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2022-03-22T22:16:20Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=f787b6821423fe0d79b63ef29ff3cb48b99af34b'/>
<id>urn:sha1:f787b6821423fe0d79b63ef29ff3cb48b99af34b</id>
<content type='text'>
- Clear pciehp cmd_busy bit when command completes in polling mode to avoid
  spurious timeouts (Liguang Zhang)

- Add quirk to work around Qualcomm hardware defect in Command Completed
  signaling (Manivannan Sadhasivam)

* pci/hotplug:
  PCI: pciehp: Add Qualcomm quirk for Command Completed erratum
  PCI: pciehp: Clear cmd_busy bit in polling mode
</content>
</entry>
<entry>
<title>Merge branch 'pci/bridge-class-codes'</title>
<updated>2022-03-22T22:16:20Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2022-03-22T22:16:20Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=fde14ee6293efc5bbde6caf7b8c6ebb2f1fb203a'/>
<id>urn:sha1:fde14ee6293efc5bbde6caf7b8c6ebb2f1fb203a</id>
<content type='text'>
- Add and use #defines for normal and subtractive PCI bridges (Pali Rohár)

- Set all 24 bits of PCI class code for iproc (Pali Rohár)

* pci/bridge-class-codes:
  PCI: iproc: Set all 24 bits of PCI class code
  PCI: Add defines for normal and subtractive PCI bridges
</content>
</entry>
</feed>
