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<title>user/sven/linux.git/drivers/phy/Makefile, branch v5.9.11</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.9.11</id>
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<updated>2020-06-29T13:18:00Z</updated>
<entry>
<title>phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver</title>
<updated>2020-06-29T13:18:00Z</updated>
<author>
<name>Anurag Kumar Vulisha</name>
<email>anurag.kumar.vulisha@xilinx.com</email>
</author>
<published>2020-06-29T12:00:53Z</published>
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<id>urn:sha1:4a33bea003144e217d8a3ae666f171dfc2e97bd6</id>
<content type='text'>
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the
high speed peripherals such as USB, SATA, PCIE, Display Port and
Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This
patch adds driver for that ZynqMP GT core.

Signed-off-by: Anurag Kumar Vulisha &lt;anurag.kumar.vulisha@xilinx.com&gt;
Signed-off-by: Laurent Pinchart &lt;laurent.pinchart@ideasonboard.com&gt;
Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>phy: Remove CONFIG_ARCH_* check for related subdir in Makefile</title>
<updated>2020-06-24T12:59:22Z</updated>
<author>
<name>Tiezhu Yang</name>
<email>yangtiezhu@loongson.cn</email>
</author>
<published>2020-05-25T13:08:58Z</published>
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<id>urn:sha1:133552bf03edbe3892767a4b64c56e3bed746374</id>
<content type='text'>
If CONFIG_ARCH_ROCKCHIP is not set but COMPILE_TEST is set, the file in
the subdir rockchip can not be built due to CONFIG_ARCH_ROCKCHIP check
in drivers/phy/Makefile.

Since the related configs in drivers/phy/rockchip/Kconfig depend on
ARCH_ROCKCHIP, so remove CONFIG_ARCH_ROCKCHIP check for subdir rockchip
in drivers/phy/Makefile.

The other CONFIG_ARCH_* about allwinner, amlogic, mediatek, renesas and
tegra have the same situation, so remove them too.

Signed-off-by: Tiezhu Yang &lt;yangtiezhu@loongson.cn&gt;
Reviewed-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Link: https://lore.kernel.org/r/1590412138-13903-2-git-send-email-yangtiezhu@loongson.cn
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>phy: intel-lgm-emmc: Add support for eMMC PHY</title>
<updated>2020-01-14T05:20:19Z</updated>
<author>
<name>Ramuthevar Vadivel Murugan</name>
<email>vadivel.muruganx.ramuthevar@linux.intel.com</email>
</author>
<published>2019-12-17T01:56:58Z</published>
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<id>urn:sha1:9227942383307f97fa6992416f73af4a23ef972c</id>
<content type='text'>
Add support for eMMC PHY on Intel's Lightning Mountain SoC.

Signed-off-by: Ramuthevar Vadivel Murugan &lt;vadivel.muruganx.ramuthevar@linux.intel.com&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@intel.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: enable compile-testing for the Lantiq PHY drivers</title>
<updated>2019-08-23T04:10:51Z</updated>
<author>
<name>Martin Blumenstingl</name>
<email>martin.blumenstingl@googlemail.com</email>
</author>
<published>2019-07-27T12:04:14Z</published>
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<id>urn:sha1:4e99276a6f7cf6cbf1d375e2da59c358ca0fd0a8</id>
<content type='text'>
Unconditionally include the lantiq subdirectory in the phy Makefile.

All drivers in there have their dependencies maintained. One of these
(optional) dependencies is COMPILE_TEST, however this can only be
evaluated when Kconfig scans the lantiq subdirectory.

Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: dphy: Add configuration helpers</title>
<updated>2018-12-12T04:31:51Z</updated>
<author>
<name>Maxime Ripard</name>
<email>maxime.ripard@bootlin.com</email>
</author>
<published>2018-12-07T13:55:31Z</published>
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<id>urn:sha1:dddc97e823033b705bbc06bc08b078200ad736a3</id>
<content type='text'>
The MIPI D-PHY spec defines default values and boundaries for most of the
parameters it defines. Introduce helpers to help drivers get meaningful
values based on their current parameters, and validate the boundaries of
these parameters if needed.

Signed-off-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: add driver for Freescale i.MX8MQ USB3 PHY</title>
<updated>2018-12-12T04:31:46Z</updated>
<author>
<name>Li Jun</name>
<email>jun.li@nxp.com</email>
</author>
<published>2018-11-15T14:12:47Z</published>
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<id>urn:sha1:efe81bea891586680a928ea5dde40eb1fff34be2</id>
<content type='text'>
This is a cleaned up port of the downstream i.MX8MQ USB3 PHY driver.

Signed-off-by: Li Jun &lt;jun.li@nxp.com&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'usb-4.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb</title>
<updated>2018-10-26T15:14:13Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2018-10-26T15:14:13Z</published>
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<id>urn:sha1:9703fc8caf36ac65dca1538b23dd137de0b53233</id>
<content type='text'>
Pull USB/PHY updates from Greg KH:
 "Here is the big USB/PHY driver patches for 4.20-rc1

  Lots of USB changes in here, primarily in these areas:

   - typec updates and new drivers

   - new PHY drivers

   - dwc2 driver updates and additions (this old core keeps getting
     added to new devices.)

   - usbtmc major update based on the industry group coming together and
     working to add new features and performance to the driver.

   - USB gadget additions for new features

   - USB gadget configfs updates

   - chipidea driver updates

   - other USB gadget updates

   - USB serial driver updates

   - renesas driver updates

   - xhci driver updates

   - other tiny USB driver updates

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'usb-4.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (229 commits)
  usb: phy: ab8500: silence some uninitialized variable warnings
  usb: xhci: tegra: Add genpd support
  usb: xhci: tegra: Power-off power-domains on removal
  usbip:vudc: BUG kmalloc-2048 (Not tainted): Poison overwritten
  usbip: tools: fix atoi() on non-null terminated string
  USB: misc: appledisplay: fix backlight update_status return code
  phy: phy-pxa-usb: add a new driver
  usb: host: add DT bindings for faraday fotg2
  usb: host: ohci-at91: fix request of irq for optional gpio
  usb/early: remove set but not used variable 'remain_length'
  usb: typec: Fix copy/paste on typec_set_vconn_role() kerneldoc
  usb: typec: tcpm: Report back negotiated PPS voltage and current
  USB: core: remove set but not used variable 'udev'
  usb: core: fix memory leak on port_dev_path allocation
  USB: net2280: Remove -&gt;disconnect() callback from net2280_pullup()
  usb: dwc2: disable power_down on rockchip devices
  usb: gadget: udc: renesas_usb3: add support for r8a77990
  dt-bindings: usb: renesas_usb3: add bindings for r8a77990
  usb: gadget: udc: renesas_usb3: Add r8a774a1 support
  USB: serial: cypress_m8: remove set but not used variable 'iflag'
  ...
</content>
</entry>
<entry>
<title>phy: add driver for Microsemi Ocelot SerDes muxing</title>
<updated>2018-10-05T21:36:44Z</updated>
<author>
<name>Quentin Schulz</name>
<email>quentin.schulz@bootlin.com</email>
</author>
<published>2018-10-04T12:22:07Z</published>
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<id>urn:sha1:51f6b410fc220d8a5a4fae00ebfd8243b6c11d4e</id>
<content type='text'>
The Microsemi Ocelot can mux SerDes lanes (aka macros) to different
switch ports or even make it act as a PCIe interface.

This adds support for the muxing of the SerDes.

Signed-off-by: Quentin Schulz &lt;quentin.schulz@bootlin.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>phy: socionext: add USB3 PHY driver for UniPhier SoC</title>
<updated>2018-09-10T08:57:13Z</updated>
<author>
<name>Kunihiko Hayashi</name>
<email>hayashi.kunihiko@socionext.com</email>
</author>
<published>2018-08-22T03:50:32Z</published>
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<id>urn:sha1:5ab43d0f86979d6741c1dda685af3e053982e03e</id>
<content type='text'>
Add a driver for PHY interface built into USB3 controller
implemented in UniPhier SoCs.
This driver supports High-Speed PHY and Super-Speed PHY.

Signed-off-by: Kunihiko Hayashi &lt;hayashi.kunihiko@socionext.com&gt;
Signed-off-by: Motoya Tanigawa &lt;tanigawa.motoya@socionext.com&gt;
Signed-off-by: Masami Hiramatsu &lt;masami.hiramatsu@linaro.org&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: Add driver for Cadence MHDP DisplayPort SD0801 PHY</title>
<updated>2018-09-10T08:55:44Z</updated>
<author>
<name>Scott Telford</name>
<email>stelford@cadence.com</email>
</author>
<published>2018-08-09T10:30:30Z</published>
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<id>urn:sha1:c8b427edc7378fa540a03d44ed61eb49cb7f64bc</id>
<content type='text'>
Add driver for the Cadence SD0801 "Torrent" PHY used with the Cadence MHDP
DisplayPort Tx controller.

Integration with the MHDP driver will be the subject of another commit.

Signed-off-by: Scott Telford &lt;stelford@cadence.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
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