<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/phy/tegra, branch v5.5.11</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.5.11</id>
<link rel='self' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.5.11'/>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/'/>
<updated>2019-10-25T12:28:13Z</updated>
<entry>
<title>phy: tegra: use regulator_bulk_set_supply_names()</title>
<updated>2019-10-25T12:28:13Z</updated>
<author>
<name>Bartosz Golaszewski</name>
<email>bgolaszewski@baylibre.com</email>
</author>
<published>2019-10-01T13:23:32Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=64d5989c1ae52407e63c6387863a75036a03e2f8'/>
<id>urn:sha1:64d5989c1ae52407e63c6387863a75036a03e2f8</id>
<content type='text'>
Use the new regulator helper instead of a for loop.

Signed-off-by: Bartosz Golaszewski &lt;bgolaszewski@baylibre.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: tegra: xusb: Add vbus override support on Tegra186</title>
<updated>2019-10-23T07:50:36Z</updated>
<author>
<name>Nagarjuna Kristam</name>
<email>nkristam@nvidia.com</email>
</author>
<published>2019-10-18T09:38:09Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=a8a24429dd1d799f1c6737779af88c1d39290a77'/>
<id>urn:sha1:a8a24429dd1d799f1c6737779af88c1d39290a77</id>
<content type='text'>
Tegra XUSB device control driver needs to control vbus override
during its operations, add API for the support.

Signed-off-by: Nagarjuna Kristam &lt;nkristam@nvidia.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: tegra: xusb: Add vbus override support on Tegra210</title>
<updated>2019-10-23T07:50:36Z</updated>
<author>
<name>Nagarjuna Kristam</name>
<email>nkristam@nvidia.com</email>
</author>
<published>2019-10-18T09:38:08Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=90767cdfea89c3ac7012035d66633b9ba839091a'/>
<id>urn:sha1:90767cdfea89c3ac7012035d66633b9ba839091a</id>
<content type='text'>
Tegra XUSB device control driver needs to control vbus override
during its operations, add API for the support.

Signed-off-by: Nagarjuna Kristam &lt;nkristam@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: tegra: xusb: Add usb3 port fake support on Tegra210</title>
<updated>2019-10-23T07:50:34Z</updated>
<author>
<name>Nagarjuna Kristam</name>
<email>nkristam@nvidia.com</email>
</author>
<published>2019-10-18T09:38:07Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=a5be28c3656af71f1c9d75381f7b86d5056da9f3'/>
<id>urn:sha1:a5be28c3656af71f1c9d75381f7b86d5056da9f3</id>
<content type='text'>
On Tegra210, usb2 only otg/peripheral ports dont work in device mode.
They need an assosciated usb3 port to work in device mode. Identify
an unused usb3 port and assign it as a fake USB3 port to USB2 only
port whose mode is otg/peripheral.

Based on work by BH Hsieh &lt;bhsieh@nvidia.com&gt;.

Signed-off-by: Nagarjuna Kristam &lt;nkristam@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: tegra: xusb: Add XUSB dual mode support on Tegra210</title>
<updated>2019-10-23T07:50:33Z</updated>
<author>
<name>Nagarjuna Kristam</name>
<email>nkristam@nvidia.com</email>
</author>
<published>2019-10-18T09:38:06Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=ac25b6e9f8d26b90694c1150b2e677aeac46ec71'/>
<id>urn:sha1:ac25b6e9f8d26b90694c1150b2e677aeac46ec71</id>
<content type='text'>
Configure the port capabilities based on usb_dr_mode settings.

Based on work by JC Kuo &lt;jckuo@nvidia.com&gt;.

Signed-off-by: Nagarjuna Kristam &lt;nkristam@nvidia.com&gt;
Reviewed-by: JC Kuo &lt;jckuo@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: tegra: xusb: remove unused variable</title>
<updated>2019-10-23T07:50:26Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2019-10-09T07:23:09Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=f466de0208e3ef6e9d28ad0b2d6a30cdd9d5052f'/>
<id>urn:sha1:f466de0208e3ef6e9d28ad0b2d6a30cdd9d5052f</id>
<content type='text'>
The local variable @priv is set but not used, can be removed

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: tegra: Add PCIe PIPE2UPHY support</title>
<updated>2019-08-13T15:01:15Z</updated>
<author>
<name>Vidya Sagar</name>
<email>vidyas@nvidia.com</email>
</author>
<published>2019-08-13T11:36:26Z</published>
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<id>urn:sha1:5dae15b21d36a2e6d7e92c6af39c33dea5c39cc3</id>
<content type='text'>
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC
interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U)
module. For each PCIe lane of a controller, there is a P2U unit
instantiated at hardware level. This driver provides support for the
programming required for each P2U that is going to be used for a PCIe
controller.

Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'phy-for-5.2-rc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next</title>
<updated>2019-07-01T10:11:43Z</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2019-07-01T10:11:43Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=90fca074897a6a069408ee99c23f6897095b6d02'/>
<id>urn:sha1:90fca074897a6a069408ee99c23f6897095b6d02</id>
<content type='text'>
Kishon writes:

phy: for 5.2-rc

  *) Move Tegra124 PLL power supplies to be enabled by xusb-tegra124
  *) Move Tegra210 PLL power supplies to be enabled by xusb-tegra210
  *) Minor fixes: fix memory leaks at error path and addresses coverity.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;

* tag 'phy-for-5.2-rc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy:
  phy: tegra: xusb: Add Tegra210 PLL power supplies
  phy: tegra: xusb: Add Tegra124 PLL power supplies
  dt-bindings: phy: tegra-xusb: List PLL power supplies
  phy: usb: phy-brcm-usb: Remove sysfs attributes upon driver removal
  phy: renesas: rcar-gen2: Fix memory leak at error paths
  phy: qcom-qusb2: fix missing assignment of ret when calling clk_prepare_enable
</content>
</entry>
<entry>
<title>phy: tegra: xusb: Add Tegra210 PLL power supplies</title>
<updated>2019-06-12T10:05:44Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-04-25T15:34:44Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=e3888cda394c72dcfd450afec1121d9777a59805'/>
<id>urn:sha1:e3888cda394c72dcfd450afec1121d9777a59805</id>
<content type='text'>
The Tegra210 SoC has four inputs that consume power in order to supply
the PLLs that drive the various USB, PCI and SATA pads.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: tegra: xusb: Add Tegra124 PLL power supplies</title>
<updated>2019-06-12T10:05:44Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-04-25T15:34:43Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=aa5452f54b9f21213364baed25a0f8241aa09050'/>
<id>urn:sha1:aa5452f54b9f21213364baed25a0f8241aa09050</id>
<content type='text'>
The Tegra124 SoC has four inputs that consume power in order to supply
the PLLs that drive the various USB, PCI and SATA pads.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
</feed>
