user/sven/linux.git/drivers/phy/ti, branch v5.4.43

phy: ti: gmii-sel: do not fail in case of gmii

2020-03-25T07:25:42Z

[ Upstream commit 58aa7729310db04ffcc022c98002dd8fcb486c58 ] The "gmii" PHY interface mode is supported on TI AM335x/437x/5xx SoCs, so don't fail if it's selected. Signed-off-by: Grygorii Strashko Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin

phy: ti: gmii-sel: fix set of copy-paste errors

2020-03-25T07:25:42Z

[ Upstream commit eefed634eb61e4094b9fb8183cb8d43b26838517 ] - under PHY_INTERFACE_MODE_MII the 'mode' func parameter is assigned instead of 'gmii_sel_mode' and it's working only because the default value 'gmii_sel_mode' is set to 0. - console outputs use 'rgmii_id' and 'mode' values to print PHY mode instead of using 'submode' value which is representing PHY interface mode now. This patch fixes above two cases. Signed-off-by: Grygorii Strashko Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin

phy: ti: gmii-sel: fix mac tx internal delay for rgmii-rxid

2020-01-26T09:01:01Z

commit 316b429459066215abb50060873ec0832efc4044 upstream. Now phy-gmii-sel will disable MAC TX internal delay for PHY interface mode "rgmii-rxid" which is incorrect. Hence, fix it by enabling MAC TX internal delay in the case of "rgmii-rxid" mode. Fixes: 92b58b34741f ("phy: ti: introduce phy-gmii-sel driver") Signed-off-by: Grygorii Strashko Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Greg Kroah-Hartman

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2019-09-20T22:45:07Z

Pull clk updates from Stephen Boyd: "We have a small collection of core framework updates this time, mostly around clk registration by clk providers and debugfs "nice to haves" for rate constraints. I'll highlight that we're now setting the clk_init_data pointer inside struct clk_hw to NULL during clk_register(), which may break some drivers that thought they could use that pointer during normal operations. That change has been sitting in next for a while now but maybe something is still broken. We'l see. Other than that the core framework changes aren't invasive and they're fixing bugs, simplifying, and making things better. On the clk driver side we got the usual addition of new SoC support, new features for existing drivers, and bug fixes scattered throughout. The biggest diffstat is the Amlogic driver that gained CPU clk support in addition to migrating to the new way of specifying clk parents. After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and clock controllers from those vendors. Core: - Drop NULL checks in clk debugfs - Add min/max rates to clk debugfs - Set clk_init_data pointer inside clk_hw to NULL after registration - Make clk_bulk_get_all() return an 'id' corresponding to clock-names - Evict parents from parent cache when they're unregistered New Drivers: - Add clock driver for i.MX8MN SoCs - Support aspeed AST2600 SoCs - Support for Mediatek MT6779 SoCs - Support qcom SM8150 GCC and RPMh clks - Support qcom QCS404 WCSS clks - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807) - Addition of clock driver for Rockchip rk3308 SoCs Updates: - Add regulator support to the cdce925 clk driver - Add support for Raspberry Pi 4 bcm2711 SoCs - Add SDIO gate support to aspeed driver - Add missing of_node_put() calls in various clk drivers - Migrate Amlogic driver to new clock parent description method - Add DVFS support to Amlogic Meson g12 - Add Amlogic Meson g12a reset support to the axg audio clock controller - Add sm1 support to the Amlogic Meson g12a clock controller - Switch i.MX8MM clock driver to platform driver - Add Hifi4 DSP related clocks for i.MX8QXP SoC - Fix Audio PLL setting and parent clock for USB - Misc i.MX8 clock driver improvements and corrections - Set floor ops for Qualcomm SD clks so that rounding works - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1 - Enable the Allwinner V3 SoC and fix the i2s clock for H6" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: Drop !clk checks in debugfs dumping clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: mvebu: ap80x: add AP807 clock support clk: mvebu: ap806: Prepare the introduction of AP807 clock support clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver clk: mvebu: ap806: be more explicit on what SaR is clk: mvebu: ap80x-cpu: add AP807 CPU clock support clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock dt-bindings: ap806: Document AP807 clock compatible dt-bindings: ap80x: Document AP807 CPU clock compatible clk: sprd: add missing kfree clk: at91: allow 24 Mhz clock as input for PLL clk: Make clk_bulk_get_all() return a valid "id" clk: actions: Fix factor clk struct member access clk: qcom: rcg: Return failure for RCG update clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h ...

phy: ti: am654-serdes: fix an use-after-free in serdes_am654_clk_register()

2019-08-26T11:50:01Z

The regmap_node variable is still being used in the syscon_node_to_regmap() call after the of_node_put() call, which may result in use-after-free. Fixes: 71e2f5c5c224 ("phy: ti: Add a new SERDES driver for TI's AM654x SoC") Signed-off-by: Wen Yang Cc: Kishon Vijay Abraham I Cc: Roger Quadros Reviewed-by: Roger Quadros Signed-off-by: Kishon Vijay Abraham I

phy: ti: am654-serdes: Don't reference clk_init_data after registration

2019-08-16T17:20:07Z

A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Roger Quadros Cc: Kishon Vijay Abraham I Signed-off-by: Stephen Boyd Link: https://lkml.kernel.org/r/20190731193517.237136-9-sboyd@kernel.org Acked-by: Kishon Vijay Abraham I

Merge tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next

2019-07-01T13:04:59Z

phy: for 5.3 *) Add a new PHY driver for Qualcomm PCIe2 PHY *) Add a new PHY driver for Mixel DPHY present in i.MX8 *) Fix Qualcomm QMP UFS PHY driver from incorrectly reporting that PHY enable failed *) Fix _BUG_ on Amlogic G12A USB3 + PCIE Combo PHY Driver due to calling a sleeping function from invalid context *) Fix WARN_ON dump on rcar-gen3-usb2 PHY driver caused due to imbalance powered flag *) Fix .cocci and sparse warnings Signed-off-by: Kishon Vijay Abraham I * tag 'phy-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: qcom-qmp: Raise qcom_qmp_phy_enable() polling delay phy: meson-g12a-usb3-pcie: disable locking for cr_regmap phy: Add driver for mixel mipi dphy found on NXP's i.MX8 SoCs dt-bindings: phy: Add documentation for mixel dphy dt-bindings: phy-pxa-usb: add bindings phy: renesas: rcar-gen3-usb2: fix imbalance powered flag phy: qcom-qmp: Drop useless msm8998_pciephy_cfg setting phy: qcom-qmp: Correct READY_STATUS poll break condition phy: ti: am654-serdes: Make serdes_am654_xlate() static phy: usb: phy-brcm-usb: Fix platform_no_drv_owner.cocci warnings phy: samsung: Use struct_size() in devm_kzalloc() phy: qcom: Add Qualcomm PCIe2 PHY driver dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY

phy: ti: am654-serdes: Make serdes_am654_xlate() static

2019-06-21T05:21:14Z

Fix sparse warning: drivers/phy/ti/phy-am654-serdes.c:250:12: warning: symbol 'serdes_am654_xlate' was not declared. Should it be static? Reported-by: Hulk Robot Signed-off-by: YueHaibing Acked-by: Roger Quadros Signed-off-by: Kishon Vijay Abraham I

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285

2019-06-05T15:36:37Z

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 of the license this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 100 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Alexios Zavras Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.918357685@linutronix.de Signed-off-by: Greg Kroah-Hartman