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<title>user/sven/linux.git/drivers/reset/Makefile, branch v5.10.207</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=v5.10.207</id>
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<updated>2020-08-18T11:01:10Z</updated>
<entry>
<title>reset: Add Raspberry Pi 4 firmware reset controller</title>
<updated>2020-08-18T11:01:10Z</updated>
<author>
<name>Nicolas Saenz Julienne</name>
<email>nsaenzjulienne@suse.de</email>
</author>
<published>2020-06-29T16:18:38Z</published>
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<id>urn:sha1:abffc82aae8745810fce5b51d9787d82d381068b</id>
<content type='text'>
Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. Introduce a reset controller capable of interfacing with
RPi4's co-processor that models these firmware initialization routines as
reset lines.

Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Reviewed-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Nicolas Saenz Julienne &lt;nsaenzjulienne@suse.de&gt;
Link: https://lore.kernel.org/r/20200629161845.6021-3-nsaenzjulienne@suse.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>reset: Add Broadcom STB RESCAL reset controller</title>
<updated>2020-01-06T09:02:03Z</updated>
<author>
<name>Jim Quinlan</name>
<email>jim2101024@gmail.com</email>
</author>
<published>2020-01-03T19:04:29Z</published>
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<id>urn:sha1:4cf176e52397853e4a4dd37e917c5eafb47ba8d1</id>
<content type='text'>
On BCM7216 there is a special purpose reset controller named RESCAL
(reset calibration) which is necessary for SATA and PCIe0/1 to operate
correctly. This commit adds support for such a reset controller to be
available.

Signed-off-by: Jim Quinlan &lt;jim2101024@gmail.com&gt;
Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>reset: intel: Add system reset controller driver</title>
<updated>2020-01-03T10:01:27Z</updated>
<author>
<name>Dilip Kota</name>
<email>eswara.kota@linux.intel.com</email>
</author>
<published>2020-01-03T10:00:18Z</published>
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<id>urn:sha1:c9aef213e38cde27d4689a5cbe25a7c1b1db9fad</id>
<content type='text'>
Add driver for the reset controller present on Intel
Gateway SoCs for performing reset management of the
devices present on the SoC. Driver also registers a
reset handler to peform the entire device reset.

Signed-off-by: Dilip Kota &lt;eswara.kota@linux.intel.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>reset: npcm: add NPCM reset controller driver</title>
<updated>2020-01-02T11:25:05Z</updated>
<author>
<name>Tomer Maimon</name>
<email>tmaimon77@gmail.com</email>
</author>
<published>2019-11-06T14:53:31Z</published>
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<id>urn:sha1:9c81b2ccf82da6e995b63e945afa882cfaa03ca9</id>
<content type='text'>
Add Nuvoton NPCM BMC reset controller driver.

Signed-off-by: Tomer Maimon &lt;tmaimon77@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>reset: Add support for resets provided by SCMI</title>
<updated>2019-08-12T11:23:02Z</updated>
<author>
<name>Sudeep Holla</name>
<email>sudeep.holla@arm.com</email>
</author>
<published>2019-07-08T08:41:08Z</published>
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<id>urn:sha1:c8ae9c2da1cc5d18b6d51d10160508a3dc3436bf</id>
<content type='text'>
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Management Interface(SCMI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

Adds support for the resets provided using SCMI protocol for performing
reset management of various devices present on the SoC. Various reset
functionalities are achieved by the means of different ARM SCMI device
operations provided by the ARM SCMI framework.

Reviewed-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into arm/drivers</title>
<updated>2019-02-15T16:21:32Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2019-02-15T16:21:04Z</published>
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<id>urn:sha1:6f2185f8e345c9023bdd030d7dae4affd6bea539</id>
<content type='text'>
Reset controller changes for v5.1

This adds the include/linux/reset directory to MAINTAINERS for reset
specific headers and adds headers for sunxi and socfpga in there to
get rid of a few extern function declarations.
There is a new reset driver for the Broadcom STB reset controller and
the i.MX7 system reset controller driver is extended to support i.MX8MQ
as well. Finally, there is a new header with reset id constants for
the Meson G12A SoC, which has a reset controller identical to Meson AXG
and thus can reuse its driver and DT bindings.

* tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux:
  dt-bindings: reset: meson: add g12a bindings
  reset: imx7: Add support for i.MX8MQ IP block variant
  reset: imx7: Add plubming to support multiple IP variants
  reset: Add Broadcom STB SW_INIT reset controller driver
  dt-bindings: reset: Add document for Broadcom STB reset controller
  reset: socfpga: declare socfpga_reset_init in a header file
  reset: sunxi: declare sun6i_reset_init in a header file
  MAINTAINERS: use include/linux/reset for reset controller related headers
  dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'zynqmp-soc-for-v5.1' of https://github.com/Xilinx/linux-xlnx into arm/drivers</title>
<updated>2019-02-15T16:16:45Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2019-02-15T16:16:17Z</published>
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<id>urn:sha1:59f527dd7a6191734f7c2049f045cbcac290efa8</id>
<content type='text'>
arm64: zynqmp: SoC changes for v5.1

- Extend firmware interface with reset, nvmem,
  power management and power domain support

- Add reset, nvmem driver, power management and
  power domain drivers
-

* tag 'zynqmp-soc-for-v5.1' of https://github.com/Xilinx/linux-xlnx:
  drivers: soc: xilinx: Add ZynqMP power domain driver
  firmware: xilinx: Add APIs to control node status/power
  dt-bindings: power: Add ZynqMP power domain bindings
  drivers: soc: xilinx: Add ZynqMP PM driver
  firmware: xilinx: Implement ZynqMP power management APIs
  dt-bindings: soc: Add ZynqMP PM bindings
  nvmem: zynqmp: Added zynqmp nvmem firmware driver
  dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
  firmware: xilinx: Add zynqmp_pm_get_chipid() API
  reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
  dt-bindings: reset: Add bindings for ZynqMP reset driver
  firmware: xilinx: Add reset API's

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.</title>
<updated>2019-01-29T13:08:40Z</updated>
<author>
<name>Nava kishore Manne</name>
<email>nava.manne@xilinx.com</email>
</author>
<published>2019-01-25T07:46:54Z</published>
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<id>urn:sha1:62f0d7dc3bae9f7ce2701d6c8cfd3d93130017af</id>
<content type='text'>
Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
The zynqmp reset-controller has the ability to reset lines
connected to different blocks and peripheral in the Soc.

Signed-off-by: Nava kishore Manne &lt;nava.manne@xilinx.com&gt;
Acked-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>reset: Add Broadcom STB SW_INIT reset controller driver</title>
<updated>2019-01-28T10:16:04Z</updated>
<author>
<name>Florian Fainelli</name>
<email>f.fainelli@gmail.com</email>
</author>
<published>2019-01-23T22:54:36Z</published>
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<id>urn:sha1:77750bc089e4508ff62f036e6e6626cf8d7384cb</id>
<content type='text'>
Add support for resetting blocks through the Linux reset controller
subsystem when reset lines are provided through a SW_INIT-style reset
controller on Broadcom STB SoCs.

Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>reset: uniphier-usb3: Rename to reset-uniphier-glue</title>
<updated>2019-01-07T15:38:51Z</updated>
<author>
<name>Kunihiko Hayashi</name>
<email>hayashi.kunihiko@socionext.com</email>
</author>
<published>2018-11-09T01:42:05Z</published>
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<id>urn:sha1:3eb8f765f5aeca6e4195246f41e534025f69eee8</id>
<content type='text'>
This driver works for controlling the reset lines including USB3
glue layer, however, this can be applied to other glue layers.
Now this patch renames the driver from "reset-uniphier-usb3" to
"reset-uniphier-glue".

At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to
CONFIG_RESET_UNIPHIER_GLUE.

Signed-off-by: Kunihiko Hayashi &lt;hayashi.kunihiko@socionext.com&gt;
Signed-off-by: Philipp Zabel &lt;p.zabel@pengutronix.de&gt;
</content>
</entry>
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