user/sven/linux.git/drivers/soc/mediatek, branch v5.16.4

ASoC: mediatek: Check for error clk pointer

2022-01-27T11:02:08Z

[ Upstream commit 9de2b9286a6dd16966959b3cb34fc2ddfd39213e ] Yes, you are right and now the return code depending on the init_clks(). Fixes: 6078c651947a ("soc: mediatek: Refine scpsys to support multiple platform") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20211222015157.1025853-1-jiasheng@iscas.ac.cn Signed-off-by: Mark Brown Signed-off-by: Sasha Levin

soc: mediatek: mmsys: Add reset controller support

2021-10-08T13:15:26Z

Among other features the mmsys driver should implement a reset controller to be able to reset different bits from their space. Cc: Jitao Shi Suggested-by: Chun-Kuang Hu Signed-off-by: Enric Balletbo i Serra Reviewed-by: Philipp Zabel Link: https://lore.kernel.org/r/20210930103105.v4.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid Signed-off-by: Matthias Brugger

soc: mediatek: add mtk mutex support for MT8192

2021-10-08T11:25:43Z

Add mtk mutex support for MT8192 SoC. Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Link: https://lore.kernel.org/r/20210930155222.5861-5-yongqiang.niu@mediatek.com Signed-off-by: Matthias Brugger

soc: mediatek: mmsys: Add mt8192 mmsys routing table

2021-09-13T08:52:13Z

mt8192 has different routing registers than mt8183 Signed-off-by: Yongqiang Niu Link: https://lore.kernel.org/r/1627894773-23872-3-git-send-email-yongqiang.niu@mediatek.com [mb: take mask into account] Signed-off-by: Matthias Brugger

soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing

2021-08-06T14:43:23Z

The UFOE (data compression engine) component needs to be enabled to have the imgtec gpu driver working. If we don't enable it we see a black screen. Looks like when we switched to use and array for setting the routing registers in commit 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") we missed to add this component in the new routing table, it was present before that commit, so fix it by adding this component in the mt8173 routing table. Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") Signed-off-by: Enric Balletbo i Serra Tested-by: Eizan Miyamoto Cc: Link: https://lore.kernel.org/r/20210625062448.3462177-1-enric.balletbo@collabora.com [mb: taking into account mask value] Signed-off-by: Matthias Brugger

soc: mediatek: mmsys: add MT8365 support

2021-08-06T14:43:23Z

Add DSI mmsys connections for the MT8365 SoC. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210519161847.3747352-3-fparent@baylibre.com [mb: take the mask field into account] Signed-off-by: Matthias Brugger

soc: mmsys: mediatek: add mask to mmsys routes

2021-08-04T17:05:46Z

SOUT has many bits and need to be cleared before set new value. Write only could do the clear, but for MOUT, it clears bits that should not be cleared. So use a mask to reset only the needed bits. this fixes HDMI issues on MT7623/BPI-R2 since 5.13 Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") Signed-off-by: Frank Wunderlich Signed-off-by: CK Hu Reviewed-by: Chun-Kuang Hu Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210729070549.5514-1-linux@fw-web.de Signed-off-by: Matthias Brugger

soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD

2021-07-12T10:26:29Z

The mfg_async power domain in mt8173 is used to power up imgtec gpu. This domain requires the da9211 regulator to be enabled before the power domain can be enabled successfully. Signed-off-by: Bilal Wasim Signed-off-by: Enric Balletbo i Serra Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210701114012.RESEND.2.I2e1bf1b589f9138ba6f89791ed9f1e9f3ddd0a5d@changeid Signed-off-by: Matthias Brugger

soc: mediatek: pm-domains: Use correct mask for bus_prot_clr

2021-07-12T10:26:28Z

When "bus_prot_reg_update" is true, the driver should use INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus protection. However, the driver does not use this mask for clearing bus protection which causes failure when booting the imgtec gpu. Corrected and tested with mt8173 chromebook. Signed-off-by: Bilal Wasim Signed-off-by: Enric Balletbo i Serra Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210701114012.RESEND.1.I27436c29c3bede46dcf86df696f48683662d1ec1@changeid Signed-off-by: Matthias Brugger

soc: mediatek: pwrap: add pwrap driver for MT8195 SoC

2021-06-03T17:41:26Z

MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger