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<title>user/sven/linux.git/drivers/soc, branch v3.18.98</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2014-10-28T21:05:07Z</updated>
<entry>
<title>soc: versatile: Add terminating entry for realview_soc_of_match</title>
<updated>2014-10-28T21:05:07Z</updated>
<author>
<name>Axel Lin</name>
<email>axel.lin@ingics.com</email>
</author>
<published>2014-10-19T15:41:00Z</published>
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<id>urn:sha1:157a1b17a5eb24f957ada8c2522cb88d9e3665fb</id>
<content type='text'>
The of_device_id table is supposed to be zero-terminated.

Signed-off-by: Axel Lin &lt;axel.lin@ingics.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2014-10-08T21:37:16Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2014-10-08T21:37:16Z</published>
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<id>urn:sha1:8b45bc892e6842115fc87c2b2a3b86a20617606a</id>
<content type='text'>
Pull ARM SoC driver updates from Arnd Bergmann:
 "These are changes for drivers that are intimately tied to some SoC and
  for some reason could not get merged through the respective subsystem
  maintainer tree.

  Most of the new code is for the Keystone Navigator driver, which is
  new base support that is going to be needed for their hardware
  accelerated network driver and other units.

  Most of the commits are for moving old code around from at91 and omap
  for things that are done in device drivers nowadays.

   - at91: move reset, poweroff, memory and clocksource code into
     drivers directories
   - socfpga: add edac driver (through arm-soc, as requested by Boris)
   - omap: move omap-intc code to drivers/irqchip
   - sunxi: added an RTC driver for sun6i
   - omap: mailbox driver related changes
   - keystone: support for the "Navigator" component
   - versatile: new reboot, led and soc drivers"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (92 commits)
  bus: arm-ccn: Fix spurious warning message
  leds: add device tree bindings for register bit LEDs
  soc: add driver for the ARM RealView
  power: reset: driver for the Versatile syscon reboot
  leds: add a driver for syscon-based LEDs
  drivers/soc: ti: fix build break with modules
  MAINTAINERS: Add Keystone Multicore Navigator drivers entry
  soc: ti: add Keystone Navigator DMA support
  Documentation: dt: soc: add Keystone Navigator DMA bindings
  soc: ti: add Keystone Navigator QMSS driver
  Documentation: dt: soc: add Keystone Navigator QMSS bindings
  rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc
  rtc: sun6i: Add sun6i RTC driver
  irqchip: omap-intc: remove unnecessary comments
  irqchip: omap-intc: correct maximum number or MIR registers
  irqchip: omap-intc: enable TURBO idle mode
  irqchip: omap-intc: enable IP protection
  irqchip: omap-intc: remove unnecesary of_address_to_resource() call
  irqchip: omap-intc: comment style cleanup
  irqchip: omap-intc: minor improvement to omap_irq_pending()
  ...
</content>
</entry>
<entry>
<title>soc: add driver for the ARM RealView</title>
<updated>2014-09-25T22:26:10Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2014-07-25T13:04:52Z</published>
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<id>urn:sha1:a2974c9c1f83e7163e855eb80c772db45bc9a291</id>
<content type='text'>
This adds a SoC driver to be used by the ARM RealView
reference boards. We create the "versatile" directory to hold
the different ARM reference designs as per the pattern of the
clk directory layout. The driver utilze the syscon to get to
the register needed. After this we can use sysfs to get at
some SoC properties on RealView DT variants like this:

&gt; cd /sysbus/soc/devices/soc0
&gt; ls
board         family        machine       power         subsystem
build         fpga          manufacturer  soc_id        uevent
&gt; cat family
Versatile
&gt; cat fpga
Multi-layer AXI
&gt; cat board
HBI-0147
&gt; cat build
03

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;

Conflicts:
	drivers/soc/Kconfig
	drivers/soc/Makefile
</content>
</entry>
<entry>
<title>soc: ti: add Keystone Navigator DMA support</title>
<updated>2014-09-24T13:49:15Z</updated>
<author>
<name>Santosh Shilimkar</name>
<email>santosh.shilimkar@ti.com</email>
</author>
<published>2014-03-30T21:29:04Z</published>
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<id>urn:sha1:88139ed030583557751e279968e13e892ae10825</id>
<content type='text'>
The Keystone Navigator DMA driver sets up the dma channels and flows for
the QMSS(Queue Manager SubSystem) who triggers the actual data movements
across clients using destination queues. Every client modules like
NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO
Engines has its own instance of packet dma hardware. QMSS has also
an internal packet DMA module which is used as an infrastructure
DMA with zero copy.

Initially this driver was proposed as DMA engine driver but since the
hardware is not typical DMA engine and hence doesn't comply with typical
DMA engine driver needs, that approach was naked. Link to that
discussion -
	https://lkml.org/lkml/2014/3/18/340

As aligned, now we pair the Navigator DMA with its companion Navigator
QMSS subsystem driver.

Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Kumar Gala &lt;galak@codeaurora.org&gt;
Cc: Olof Johansson &lt;olof@lixom.net&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Grant Likely &lt;grant.likely@linaro.org&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Sandeep Nair &lt;sandeep_n@ti.com&gt;
Signed-off-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
</content>
</entry>
<entry>
<title>soc: ti: add Keystone Navigator QMSS driver</title>
<updated>2014-09-24T13:49:14Z</updated>
<author>
<name>Sandeep Nair</name>
<email>sandeep_n@ti.com</email>
</author>
<published>2014-02-28T15:47:50Z</published>
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<id>urn:sha1:41f93af900a20d1a0a358b522b5129c89677e9dc</id>
<content type='text'>
The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
the main hardware sub system which forms the backbone of the Keystone
Multi-core Navigator. QMSS consist of queue managers, packed-data structure
processors(PDSP), linking RAM, descriptor pools and infrastructure
Packet DMA.

The Queue Manager is a hardware module that is responsible for accelerating
management of the packet queues. Packets are queued/de-queued by writing or
reading descriptor address to a particular memory mapped location. The PDSPs
perform QMSS related functions like accumulation, QoS, or event management.
Linking RAM registers are used to link the descriptors which are stored in
descriptor RAM. Descriptor RAM is configurable as internal or external memory.

The QMSS driver manages the PDSP setups, linking RAM regions,
queue pool management (allocation, push, pop and notify) and descriptor
pool management. The specifics on the device tree bindings for
QMSS can be found in:
	Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt

Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Kumar Gala &lt;galak@codeaurora.org&gt;
Cc: Olof Johansson &lt;olof@lixom.net&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Grant Likely &lt;grant.likely@linaro.org&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Sandeep Nair &lt;sandeep_n@ti.com&gt;
Signed-off-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
</content>
</entry>
<entry>
<title>drivers/soc: qcom: do not disable the iface clock in probe</title>
<updated>2014-09-24T04:38:32Z</updated>
<author>
<name>Srinivas Kandagatla</name>
<email>srinivas.kandagatla@linaro.org</email>
</author>
<published>2014-09-23T19:20:54Z</published>
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<id>urn:sha1:fa9eb3241895d2771b87f20dd23b40de664c5e4e</id>
<content type='text'>
since commit 31964ffebbb9 ("tty: serial: msm: Remove direct access to GSBI")'
serial hangs if earlyprintk are enabled.

This hang is noticed only when the GSBI driver is probed and all the
earlyprintks before gsbi probe are seen on the console.
The reason why it hangs is because GSBI driver disables hclk in its
probe function without realizing that the serial IP might be in use by
a bootconsole. As gsbi driver disables the clock in probe the
bootconsole locks up.

Turning off hclk's could be dangerous if there are system components
like earlyprintk using the hclk.

This patch fixes the issue by delegating the clock management to
probe and remove functions in gsbi rather than disabling the clock in probe.

More detailed problem description can be found here:
http://www.spinics.net/lists/linux-arm-msm/msg10589.html

Tested-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Convert PMC to a driver</title>
<updated>2014-07-17T12:58:43Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T11:19:06Z</published>
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<id>urn:sha1:7232398abc6a7186e315425638c367d50c674718</id>
<content type='text'>
This commit converts the PMC support code to a platform driver. Because
the boot process needs to call into this driver very early, also set up
a minimal environment via an early initcall.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Set up in early initcall</title>
<updated>2014-07-17T12:58:42Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-11T09:13:30Z</published>
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<id>urn:sha1:24fa5af81059af90c723bec6aacc3cd2b2809d14</id>
<content type='text'>
Rather than rely on explicit initialization order called from SoC setup
code, use a plain initcall and rely on initcall ordering to take care of
dependencies.

This driver exposes some functionality (querying the chip ID) needed at
very early stages of the boot process. An early initcall is good enough
provided that some of the dependencies are deferred to later stages. To
make sure any abuses are easily caught, output a warning message if the
chip ID is queried while it can't be read yet.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Implement runtime check for Tegra SoCs</title>
<updated>2014-07-17T12:58:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-07-16T12:01:44Z</published>
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<id>urn:sha1:a2686766c81e18fb1ab9375cf5d3cbd54a3bed2c</id>
<content type='text'>
Subsequent patches will move some of the initialization code from SoC
setup code to regular initcalls. To prevent breakage on other SoCs in
multi-platform builds, these initcalls need to check that they indeed
run on Tegra.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: fix dummy functions</title>
<updated>2014-07-17T12:38:29Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-06-16T21:05:04Z</published>
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<id>urn:sha1:2fa937a767bd0933dfe6017cabd038ce52594171</id>
<content type='text'>
The Tegra fuse header's dummy functions for the case where Tegra20 is
disabled are inconsistent with the correct prototypes, and have some
syntax errors. Fix these. While at it, fix the indentation level of
the dummy function bodies.

Fixes: 783c8f4c8445 ("soc/tegra: Add efuse driver for Tegra")
Cc: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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