user/sven/linux.git/drivers/spi/Makefile, branch v3.14.78

spi: bcm63xx-hsspi: add bcm63xx HSSPI driver

2013-12-04T13:29:13Z

Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs. It does feature some new modes like 3-wire or dual spi, but neither of it is currently implemented. Signed-off-by: Jonas Gorski Signed-off-by: Mark Brown

Merge remote-tracking branch 'spi/topic/qspi' into spi-next

2013-09-01T12:49:06Z

Merge remote-tracking branch 'spi/topic/efm32' into spi-next

2013-09-01T12:48:53Z

Merge remote-tracking branch 'spi/topic/dspi' into spi-next

2013-09-01T12:48:52Z

spi/qspi: Add qspi flash controller

2013-08-22T12:08:06Z

The patch add basic support for the quad spi controller. QSPI is a kind of spi module that allows single, dual and quad read access to external spi devices. The module has a memory mapped interface which provide direct interface for accessing data form external spi devices. The patch will configure controller clocks, device control register and for defining low level transfer apis which will be used by the spi framework to transfer data to the slave spi device(flash in this case). Test details: ------------- Tested this on dra7 board. Test1: Ran mtd_stesstest for 40000 iterations. - All iterations went through without failure. Test2: Use mtd utilities: - flash_erase to erase the flash device - mtd_debug read to read data back. - mtd_debug write to write to the data flash. diff between the write and read data shows zero. Acked-by: Felipe Balbi Reviewed-by: Felipe Balbi Signed-off-by: Sourav Poddar Signed-off-by: Mark Brown

spi:Add Freescale DSPI driver for Vybrid VF610 platform

2013-08-22T10:33:13Z

The serial peripheral interface (SPI) module implemented on Freescale Vybrid platform provides a synchronous serial bus for communication between Vybrid and the external peripheral device. The SPI supports full-duplex, three-wire synchronous transfer, has TX/RX FIFO with depth of four entries. This driver is the SPI master mode driver and has been tested on Vybrid VF610TWR board. Signed-off-by: Alison Wang Signed-off-by: Chao Fu Signed-off-by: Mark Brown

spi: new controller driver for efm32 SoCs

2013-08-09T16:32:57Z

Signed-off-by: Uwe Kleine-König Signed-off-by: Mark Brown

spi: add spi controller v3 master driver for Blackfin

2013-07-15T10:30:28Z

New spi controller(version 3) is integrated into Blackfin 60x processor. Comparing to bf5xx spi controller, we support 32 bits word size and independent receive and transmit DMA channels now. Also mode 0 and 2 (CPHA = 0) can get fully supported becasue cs line may be controlled by the software. Signed-off-by: Scott Jiang Signed-off-by: Mark Brown

spi/tegra114: add spi driver

2013-04-07T09:08:00Z

Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller is different than the older SoCs SPI controller in internal design as well as register interface. This driver supports the: - non DMA based transfer for smaller transfer i.e. less than FIFO depth. - APB DMA based transfer for larger transfer i.e. more than FIFO depth. - Clock gating through runtime PM callbacks. - registration through DT only. Signed-off-by: Laxman Dewangan Reviewed-by: Stephen Warren Signed-off-by: Grant Likely

spi/spi-fsl-spi: Make driver usable in CPU mode outside of an FSL_SOC environment

2013-04-07T09:07:54Z

This makes the spi-fsl-spi driver usable in CPU mode outside of an FSL_SOC and even an powerpc environment by moving CPM mode functionality to a separate file that is only compiled and linked in an FSL_SOC environment and adding some ifdefs to hide types and functions or provide alternatives. For devicetree probing a "clock-frequency" property is used for clock frequency instead of calls to FSL_SOC-specific functions. Acked-by: Anton Vorontsov Signed-off-by: Andreas Larsson Signed-off-by: Grant Likely