<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/drivers/ufs, branch next/master</title>
<subtitle>Linux Kernel
</subtitle>
<id>https://git.stealer.net/cgit.cgi/user/sven/linux.git/atom?h=next%2Fmaster</id>
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<updated>2026-04-09T02:27:16Z</updated>
<entry>
<title>scsi: ufs: core: Disable timestamp for Kioxia THGJFJT0E25BAIP</title>
<updated>2026-04-09T02:27:16Z</updated>
<author>
<name>Aaron Kling</name>
<email>webgeek1234@gmail.com</email>
</author>
<published>2026-04-03T18:41:34Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=e423f1c7195645e18945fba0bd8f0a32e39286e7'/>
<id>urn:sha1:e423f1c7195645e18945fba0bd8f0a32e39286e7</id>
<content type='text'>
Kioxia has another product that does not support the qTimestamp
attribute.

Signed-off-by: Aaron Kling &lt;webgeek1234@gmail.com&gt;
Reviewed-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Link: https://patch.msgid.link/20260403-thgjfjt0e25baip-no-timestamp-v1-1-1ddb34225133@gmail.com
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: core: Make the header files self-contained</title>
<updated>2026-04-03T01:26:44Z</updated>
<author>
<name>Bart Van Assche</name>
<email>bvanassche@acm.org</email>
</author>
<published>2026-04-01T20:25:01Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=6daa8dd037459a1d1b105bd1008fa2a32f8708e5'/>
<id>urn:sha1:6daa8dd037459a1d1b105bd1008fa2a32f8708e5</id>
<content type='text'>
Add the include directives and forward declarations that are missing
from the UFS core header files. This prevents compilation failures if
include directives are reordered.

Signed-off-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Link: https://patch.msgid.link/20260401202506.1445324-4-bvanassche@acm.org
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: core: Remove an include directive from ufshcd-crypto.h</title>
<updated>2026-04-03T01:26:44Z</updated>
<author>
<name>Bart Van Assche</name>
<email>bvanassche@acm.org</email>
</author>
<published>2026-04-01T20:25:00Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=efa1f6a9d7ce9246cb98c85335bba6a797e17584'/>
<id>urn:sha1:efa1f6a9d7ce9246cb98c85335bba6a797e17584</id>
<content type='text'>
Nothing in the ufshcd-crypto.h header file depends on the ufshcd-priv.h
header file. Hence, stop including that header file. This include
directive was introduced by commit 4bc26113c603 ("scsi: ufs: Split the
ufshcd.h header file").

Signed-off-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Link: https://patch.msgid.link/20260401202506.1445324-3-bvanassche@acm.org
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: core: Add a comment block above ufshcd_mcq_compl_all_cqes_lock()</title>
<updated>2026-04-03T01:26:44Z</updated>
<author>
<name>Bart Van Assche</name>
<email>bvanassche@acm.org</email>
</author>
<published>2026-04-01T20:24:59Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=1373df88d53594a32534fd8960c51d1d09be8ecb'/>
<id>urn:sha1:1373df88d53594a32534fd8960c51d1d09be8ecb</id>
<content type='text'>
Document the aspects of ufshcd_mcq_compl_all_cqes_lock() that are
nontrivial in a comment block above this function.

Signed-off-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Reviewed-by: Peter Wang &lt;peter.wang@mediatek.com&gt;
Link: https://patch.msgid.link/20260401202506.1445324-2-bvanassche@acm.org
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: ufs-qcom: Fix spelling mistake "retore" -&gt; "restore"</title>
<updated>2026-04-03T01:15:21Z</updated>
<author>
<name>Colin Ian King</name>
<email>colin.i.king@gmail.com</email>
</author>
<published>2026-03-31T15:30:49Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=23c29ca113e3838e9c8473c65dbc147bd058d757'/>
<id>urn:sha1:23c29ca113e3838e9c8473c65dbc147bd058d757</id>
<content type='text'>
There is a spelling mistake in a dev_err() message. Fix it.

Signed-off-by: Colin Ian King &lt;colin.i.king@gmail.com&gt;
Reviewed-by: Manivannan Sadhasivam &lt;mani@kernel.org&gt;
Link: https://patch.msgid.link/20260331153049.1344957-1-colin.i.king@gmail.com
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 7.0/scsi-fixes into 7.1/scsi-staging</title>
<updated>2026-04-03T00:31:22Z</updated>
<author>
<name>Martin K. Petersen</name>
<email>martin.petersen@oracle.com</email>
</author>
<published>2026-04-03T00:31:22Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=fc0a1d05e494fd218a51e46f6664d1e14d4327ea'/>
<id>urn:sha1:fc0a1d05e494fd218a51e46f6664d1e14d4327ea</id>
<content type='text'>
Pull in fixes to resolve mpi3mr merge conflict.

Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "scsi: ufs: Add TX Equalization support for UFS 5.0"</title>
<updated>2026-03-27T21:21:28Z</updated>
<author>
<name>Martin K. Petersen</name>
<email>martin.petersen@oracle.com</email>
</author>
<published>2026-03-27T21:21:28Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=2dfb80cc3580dc02be83246bcd5446e6f3a231b9'/>
<id>urn:sha1:2dfb80cc3580dc02be83246bcd5446e6f3a231b9</id>
<content type='text'>
Can Guo &lt;can.guo@oss.qualcomm.com&gt; says:

Hi,

The UFS v5.0 and UFSHCI v5.0 standards have published, introducing support
for HS-G6 (46.6 Gbps per lane) through the new UniPro V3.0 interconnect
layer and M-PHY V6.0 physical layer specifications. To achieve reliable
operation at these higher speeds, UniPro V3.0 introduces TX Equalization
and Pre-Coding mechanisms that are essential for signal integrity.

This patch series implements TX Equalization support in the UFS core
driver as specified in UFSHCI v5.0, along with the necessary vendor
operations and a reference implementation for Qualcomm UFS host
controllers.

Background
==========

TX Equalization is a signal conditioning technique that compensates for
channel impairments at high data rates (HS-G4 through HS-G6). It works
by adjusting two key parameters:

- PreShoot: Pre-emphasis applied before the main signal transition
- DeEmphasis: De-emphasis applied after the main signal transition

UniPro V3.0 defines TX Equalization Training (EQTR) procedure to
automatically discover optimal TX Equalization settings. The EQTR
procedure:

1. Starts from the most reliable link state (HS-G1)
2. Iterates through all possible PreShoot and DeEmphasis combinations
3. Evaluates signal quality using Figure of Merit (FOM) measurements
4. Selects the best settings for both host and device TX lanes

For HS-G6, Pre-Coding is also introduced to further improve signal
quality. Pre-Coding must be enabled on both transmitter and receiver
when the RX_FOM indicates it is required.

Implementation Overview
=======================

The implementation follows the UFSHCI v5.0 specification and consists of:

Core Infrastructure (Patches 1-6):
- New vops callback negotiate_pwr_mode() to allow vendors to negotiate
  power mode parameters before applying TX Equalization settings
- Support for HS-G6 gear enumeration
- Complete TX EQTR procedure implementation in ufs-txeq.c
- Debugfs interface for TX Equalization parameter inspection and manual
  retraining
- Module parameters for adaptive TX Equalization control

Qualcomm Implementation (Patches 7-11):
- PHY-specific configurations for TX EQTR procedure
- Vendor-specific FOM measurement support
- TX Equalization settings application
- Enable TX Equalization for HW version 0x7 and onwards

The implementation is designed to be vendor-agnostic, with platform-
specific details handled through the vops callbacks. Other vendors can
add support by implementing the three new vops:

- tx_eqtr_notify(): Called before/after TX EQTR for vendor setup
- apply_tx_eqtr_settings(): Apply vendor-specific PHY configurations
- get_rx_fom(): Retrieve vendor-specific FOM measurements if needed

Module Parameters
=================

The implementation provides several module parameters for flexibility:

- use_adaptive_txeq: Enable/disable adaptive TX Equalization (default: false)
- adaptive_txeq_gear: Minimum gear for adaptive TX EQ (default: HS-G6)
- use_txeq_presets: Use only the 8 standaird presets (default: false)
- txeq_presets_selected[]: Select specific presets for EQTR

Testing
=======

This patch series has been tested on Qualcomm platforms with UFS 5.0
devices, validating:

- Successful TX EQTR completion for HS-G6
- Proper FOM evaluation and optimal settings selection
- Pre-Coding enablement for HS-G6
- Power mode changes with TX Equalization settings applied
- Report of TX Equalization settings via debugfs entries
- Report of TX EQTR histories via debug entries (see next section)
- Re-training TX Equalization via debugfs entry

Example of TX EQTR history
==========================

Device TX EQTR record summary -
Target Power Mode: HS-G6, Rate-B
Most recent record index: 2
Most recent record timestamp: 219573378 us

TX Lane 0 FOM - PreShoot\DeEmphasis
\       0        1        2        3        4        5        6        7
0      50       70       65        -        -        -        -        x
1       x        x        x        x        x        x        x        x
2     100       90       70        -        -        -        -        x
3       x        x        x        x        x        x        x        x
4      95       90        -        -        -        -        -        x
5       -        -        -        -        -        -        -        x
6       x        x        x        x        x        x        x        x
7       x        x        x        x        x        x        x        x

TX Lane 1 FOM - PreShoot\DeEmphasis
\       0        1        2        3        4        5        6        7
0      50       70       60        -        -        -        -        x
1       x        x        x        x        x        x        x        x
2     100       80       65        -        -        -        -        x
3       x        x        x        x        x        x        x        x
4      95       85        -        -        -        -        -        x
5       -        -        -        -        -        -        -        x
6       x        x        x        x        x        x        x        x
7       x        x        x        x        x        x        x        x

Patch Structure
===============

Patches 1-3: Preparatory changes for power mode negotiation and HS-G6
Patch 4: Core TX Equalization and EQTR implementation
Patches 5-7: Debugfs support for TX Equalization
Patches 8-12: Qualcomm vendor implementation

Next
====

One more series has been developed to enhance TX Equalization support,
which will be submitted for review after this series is accepted:

- Provide board specific (static) TX Equalization settings from DTS
- Parse static TX Equalization settings from DTS if provided
- Apply static TX Equalization settings if use_adaptive_txeq is disabled
- Add support for UFS v5.0 attributes qTxEQGnSettings &amp; wTxEQGnSettingsExt
- Enable persistent storage and retrieval of optimal TX Equalization settings

Link: https://patch.msgid.link/20260325152154.1604082-1-can.guo@oss.qualcomm.com
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: ufs-qcom: Enable TX Equalization</title>
<updated>2026-03-27T21:20:30Z</updated>
<author>
<name>Can Guo</name>
<email>can.guo@oss.qualcomm.com</email>
</author>
<published>2026-03-25T15:21:54Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=57b7943fd87f086a3497ecbecc502b7418ed4ab8'/>
<id>urn:sha1:57b7943fd87f086a3497ecbecc502b7418ed4ab8</id>
<content type='text'>
Enable TX Equalization for hosts with HW version 0x7 and onwards.

Reviewed-by: Bean Huo &lt;beanhuo@micron.com&gt;
Reviewed-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Signed-off-by: Can Guo &lt;can.guo@oss.qualcomm.com&gt;
Reviewed-by: Peter Wang &lt;peter.wang@mediatek.com&gt;
Link: https://patch.msgid.link/20260325152154.1604082-13-can.guo@oss.qualcomm.com
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: ufs-qcom: Implement vops apply_tx_eqtr_settings()</title>
<updated>2026-03-27T21:20:30Z</updated>
<author>
<name>Can Guo</name>
<email>can.guo@oss.qualcomm.com</email>
</author>
<published>2026-03-25T15:21:53Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=16cbdc8308776270d76340cd52ac63ac4fbf9968'/>
<id>urn:sha1:16cbdc8308776270d76340cd52ac63ac4fbf9968</id>
<content type='text'>
On some platforms, when Host Software triggers TX Equalization Training, HW
does not take TX EQTR settings programmed in PA_TxEQTRSetting, instead HW
takes TX EQTR settings from PA_TxEQG1Setting. Implement vops
apply_tx_eqtr_setting() to work around it by programming TX EQTR settings
to PA_TxEQG1Setting during TX EQTR procedure.

Reviewed-by: Bean Huo &lt;beanhuo@micron.com&gt;
Reviewed-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Signed-off-by: Can Guo &lt;can.guo@oss.qualcomm.com&gt;
Reviewed-by: Peter Wang &lt;peter.wang@mediatek.com&gt;
Link: https://patch.msgid.link/20260325152154.1604082-12-can.guo@oss.qualcomm.com
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
<entry>
<title>scsi: ufs: ufs-qcom: Implement vops get_rx_fom()</title>
<updated>2026-03-27T21:20:30Z</updated>
<author>
<name>Can Guo</name>
<email>can.guo@oss.qualcomm.com</email>
</author>
<published>2026-03-25T15:21:52Z</published>
<link rel='alternate' type='text/html' href='https://git.stealer.net/cgit.cgi/user/sven/linux.git/commit/?id=26605db7604deb18cf004cf3ad51e72e5d9b7add'/>
<id>urn:sha1:26605db7604deb18cf004cf3ad51e72e5d9b7add</id>
<content type='text'>
On some platforms, host's M-PHY RX_FOM Attribute always reads 0, meaning SW
cannot rely on Figure of Merit (FOM) to identify the optimal TX
Equalization settings for device's TX Lanes. Implement the vops
ufs_qcom_get_rx_fom() such that SW can utilize the UFS Eye Opening Monitor
(EOM) to evaluate the TX Equalization settings for device's TX Lanes.

Reviewed-by: Bean Huo &lt;beanhuo@micron.com&gt;
Reviewed-by: Bart Van Assche &lt;bvanassche@acm.org&gt;
Signed-off-by: Can Guo &lt;can.guo@oss.qualcomm.com&gt;
Reviewed-by: Peter Wang &lt;peter.wang@mediatek.com&gt;
Link: https://patch.msgid.link/20260325152154.1604082-11-can.guo@oss.qualcomm.com
Signed-off-by: Martin K. Petersen &lt;martin.petersen@oracle.com&gt;
</content>
</entry>
</feed>
