<feed xmlns='http://www.w3.org/2005/Atom'>
<title>user/sven/linux.git/include/asm-sparc/cache.h, branch v2.6.16.45</title>
<subtitle>Linux Kernel
</subtitle>
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<updated>2006-01-09T04:13:39Z</updated>
<entry>
<title>[PATCH] Kill L1_CACHE_SHIFT_MAX</title>
<updated>2006-01-09T04:13:39Z</updated>
<author>
<name>Ravikiran G Thirumalai</name>
<email>kiran@scalex86.org</email>
</author>
<published>2006-01-08T09:01:28Z</published>
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<id>urn:sha1:1fd73c6b6737b7e6eacac1b00dac16e7540c3cb1</id>
<content type='text'>
Kill L1_CACHE_SHIFT from all arches.  Since L1_CACHE_SHIFT_MAX is not used
anymore with the introduction of INTERNODE_CACHE, kill L1_CACHE_SHIFT_MAX.

Signed-off-by: Ravikiran Thirumalai &lt;kiran@scalex86.org&gt;
Signed-off-by: Shai Fultheim &lt;shai@scalex86.org&gt;
Signed-off-by: Andi Kleen &lt;ak@suse.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@osdl.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@osdl.org&gt;
</content>
</entry>
<entry>
<title>[SPARC]: "extern inline" doesn't make much sense.</title>
<updated>2005-10-04T00:37:02Z</updated>
<author>
<name>Adrian Bunk</name>
<email>bunk@stusta.de</email>
</author>
<published>2005-10-04T00:37:02Z</published>
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<id>urn:sha1:3115624eda34d0f4e673fc6bcea36b7ad701ee33</id>
<content type='text'>
Signed-off-by: Adrian Bunk &lt;bunk@stusta.de&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[PATCH] Clean up __cacheline_aligned</title>
<updated>2004-02-26T02:07:47Z</updated>
<author>
<name>Alexander Viro</name>
<email>viro@parcelfarce.linux.theplanet.co.uk</email>
</author>
<published>2004-02-26T02:07:47Z</published>
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<id>urn:sha1:7265df88a1fc37644ea0b4dddcc8ce4f9b227ee4</id>
<content type='text'>
arm-26, ppc, sparc, sparc64 and sh have per-arch definitions of
__cacheline_aligned that are identical to default.  And yes, removal is
safe - all users of __cacheline_aligned actually pull linux/cache.h in.
</content>
</entry>
<entry>
<title>[PATCH] add L1_CACHE_SHIFT_MAX</title>
<updated>2002-08-28T04:04:02Z</updated>
<author>
<name>Andrew Morton</name>
<email>akpm@zip.com.au</email>
</author>
<published>2002-08-28T04:04:02Z</published>
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<id>urn:sha1:f9da78fb663680455bd763c6b8fbc5af34beb1f2</id>
<content type='text'>
zone-&gt;lock and zone-&gt;lru_lock are two of the hottest locks in the
kernel.  Their usage patterns are quite independent.  And they have
just been put into the same structure.  It is essential that they not
fall into the same cacheline.

That could be fixed by padding with L1_CACHE_BYTES.  But the problem
with this is that a kernel which was configured for (say) a PIII will
perform poorly on SMP PIV.  This will cause problems for kernel
vendors.  For example, RH currently ship PII and Athlon binaries.  To
get best SMP performance they will end up needing to ship a lot of
differently configured kernels.

To solve this we need to know, at compile time, the maximum L1 size
which this kernel will ever run on.

This patch adds L1_CACHE_SHIFT_MAX to every architecture's cache.h.

Of course it'll break when newer chips come out with increased
cacheline sizes.   Better suggestions are welcome.
</content>
</entry>
<entry>
<title>Sparc build fixes:</title>
<updated>2002-07-12T19:03:43Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@nuts.ninka.net</email>
</author>
<published>2002-07-12T19:03:43Z</published>
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<id>urn:sha1:cd26908d46b51959f3d4aef085fefa43959e9b94</id>
<content type='text'>
- Define L1_CACHE_SHIFT for quota sake
- Fix FC4/PLUTO build, request is a pointer in scsi_cmnd now.
- Make binfmt_elf32 build properly wrt. jiffies_to_foo changes.
</content>
</entry>
<entry>
<title>Import changeset</title>
<updated>2002-02-05T01:40:40Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@athlon.transmeta.com</email>
</author>
<published>2002-02-05T01:40:40Z</published>
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<id>urn:sha1:7a2deb32924142696b8174cdf9b38cd72a11fc96</id>
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